Infineon Technologies Americas Corp.

International Rectifier Corporation

Infineon Technologies Ag

Infineon Technologies Austria Ag

International Business Machines Corporation

Eung San Cho

Chuan Cheah

Andrew Neil Sawle

Danny Clavette

Dan Clavette

Mark Pavier

Daniel Cutler

Petteri Palm

Saverio Trotta

Ashutosh Baheti

Darryl Galipeau

Parviz Parto

Josef Hoeglauer

Tomasz Naeve

Ralf Otremba

Markus Dinkel

Dean Fernando

Fabian Schnoy

Kevin Moody

Tim Philips

Thorsten Meyer

Klaus Schiess

Oliver Haeberlen

Gerhard Prechtl

Xaver Schloegel

Gilberto Curatola

Wolfgang Furtner

Thomas Behrens

Robert Fehler

Carlo Marbella

Urban Medic

Swee Guan Chan

Navas Khan Oratti Kalandar

Jobelito Anjao Guanzon

Aida Abaca

Jobel A Guanzon

This disclosure includes multiple assemblies, sub-assemblies, etc., as well as one or more methods of fabricating same. For example, a first assembly includes a first circuit board. The first circuit board further includes first connector elements disposed on a first edge of the first circuit board and second connector elements disposed on a second edge of the first circuit board. The first edge may be disposed substantially opposite the second edge on the first circuit board. The apparatus may further include first circuitry affixed to the first circuit board. The first edge of the first circuit board aligns with a first axial end of the first circuitry and the second edge of the first circuit board aligns with a second axial end of the first circuitry. The first assembly is used to fabricate a second assembly.

Circuit and connector element alignment, circuit board assemblies

A semiconductor device comprises a semiconductor chip comprising a radio frequency (RF) circuit, a feedline structure coupled to the RF circuit, and an antenna structure comprising a main body stretching along a direction orthogonal to at least one side of a front side and a backside of the semiconductor device, wherein the antenna structure is coupled to the RF circuit through the feedline structure.

Antenna package with via structure and method of formation thereof

A semiconductor device includes a semiconductor die comprising a radio frequency (RF) circuit, a first dielectric layer disposed over a first surface of the semiconductor die, an antenna layer disposed over a surface of the first dielectric layer, and an antenna feeding structure coupling the antenna layer to the RF circuit of the semiconductor die, wherein the semiconductor die comprises a via, and the antenna feeding structure comprises a first portion arranged within the opening of the semiconductor die and extending to the first surface of the semiconductor die, and a second portion arranged through the first dielectric layer.

Antenna apparatus and fabrication method

A method of forming a semiconductor package includes producing a package substrate that includes an interior laminate layer, a first metallization layer disposed below the interior laminate layer, and a second metallization layer disposed above the interior laminate layer, providing a first load terminal on a first surface of the first semiconductor die and a second load terminal on a second surface of the first semiconductor die; and a liner of dielectric material on the first semiconductor die; providing a liner of dielectric material on the first semiconductor die; embedding the first semiconductor die within the interior laminate layer such that the first surface of the first semiconductor die faces the second metallization layer, and wherein the liner of dielectric material is disposed on a corner of the first semiconductor die that is between the first and second load terminals of the first semiconductor die.

Embedded package with electrically isolating dielectric liner

A semiconductor package includes: an electrically insulating core and an electrically conductive first via extending through a periphery region of the core, the core having glass fibres interwoven with epoxy material and one or more regions where the glass fibres are exposed from the epoxy material; a power semiconductor die embedded in an opening in the core and having a first load terminal bond pad which faces a same direction as a first side of the core, a second load terminal bond pad which faces a same direction as a second side of the core, and a control terminal bond pad; a resin that encases the power semiconductor die; a first contact pad plated on the first via at the second side of the core; and a second contact pad plated on the first load terminal bond pad of the power semiconductor die at the first side of the core.

Semiconductor package having an electrically insulating core with exposed glass fibres

A semiconductor assembly includes a semiconductor package that includes first and second transistor dies embedded within a package body, the first and second transistor dies being arranged laterally side by side within the package body such that a first load terminal of the first transistor die faces an upper surface of the package body and such that a second load terminal of the second transistor die faces the upper surface of the package body, and a discrete capacitor mounted on the semiconductor package such that a first terminal of the discrete capacitor is directly over and electrically connected to the first load terminal of the first semiconductor die and such that a second terminal of the discrete capacitor is directly over and electrically connected with the second load terminal of the second semiconductor die.

Semiconductor package with low parasitic connection to passive device

A semiconductor device includes a substrate comprising an antenna and a conductive feature; an integrated circuit (IC) die attached to the substrate and comprising a radio frequency (RF) circuit; and a flexible circuit integrated with the substrate, where the flexible circuit is electrically coupled to the IC die and the substrate, a first portion of the flexible circuit being disposed between opposing sidewalls of the substrate, a second portion of the flexible circuit extending beyond the opposing sidewalls of the substrate, the second portion of the flexible circuit comprising an electrical connector at a distal end.

Semiconductor device with embedded flexible circuit

A semiconductor package includes a package substrate that includes an interior laminate layer, a first metallization layer disposed below the interior laminate layer, and a second metallization layer disposed above the interior laminate layer, a first semiconductor die that includes a first load terminal disposed on a first surface of the first semiconductor die and a second load terminal disposed on a second surface of the first semiconductor die that is opposite from the first surface of the first semiconductor die, and a liner of dielectric material on the first semiconductor die, wherein the first semiconductor die is embedded within the interior laminate layer such that the first surface of the first semiconductor die faces the second metallization layer, and wherein the liner of dielectric material is disposed on a corner of the first semiconductor die that is between the first and second load terminals of the first semiconductor die.

A method includes: arranging a semiconductor device on a redistribution substrate, the device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, the redistribution substrate having an insulating board having a first major surface and a second major surface having solderable contact pads, so that the first power electrode is arranged on a first conductive pad and the control electrode is arranged on a second conductive pad on the first major surface; arranging a contact clip such that a web portion is arranged on the second power electrode and a peripheral rim portion is arranged on a third conductive pad on the first major surface; and electrically coupling the first power electrode, control electrode and peripheral rim portion to the respective conductive pads and electrically coupling the web portion to the second power electrode.

Method of fabricating a semiconductor package

A semiconductor package includes: an insulating substrate having opposing first and second main sides; a power semiconductor die embedded in, and thinner than or a same thickness as, the substrate, and including a first load terminal bond pad at a first side which faces a same direction as the substrate first main side, a second load terminal bond pad at a second side which faces a same direction as the substrate second main side, and a control terminal bond pad; electrically conductive first vias extending through the substrate in a periphery region; a first metallization connecting the first load terminal bond pad to the first vias at the substrate first main side; solderable first contact pads at the substrate second main side and formed by the first vias; and a solderable second contact pad at the substrate second main side and formed by the second load terminal die bond pad.

Semiconductor package having a solderable contact pad formed by a load terminal bond pad of a power semiconductor die

Semiconductor packages described herein include a thermal capacitor designed to absorb transient heat pulses from a power semiconductor die and subsequently release the transient heat pulses to a surrounding environment, and/or a recessed pad feature. Corresponding methods of production are also described.

Semiconductor packages and methods of manufacturing thereof

A packaged half-bridge circuit includes a carrier having a dielectric core and a first layer of metallization formed on an upper surface of the carrier, first and second semiconductor chips, each including a first terminal, a second terminal, and a control terminal, and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier. The conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips.

Space efficient and low parasitic half bridge

In an embodiment, a semiconductor package includes a package footprint having a plurality of solderable contact pads, a semiconductor device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, a redistribution substrate having an insulating board, wherein the first power electrode and the control electrode are mounted on a first major surface of the insulating board and the solderable contact pads of the package footprint are arranged on a second major surface of the insulating board, and a contact clip having a web portion and one or more peripheral rim portions. The web portion is mounted on and electrically coupled to the second power electrode and the peripheral rim portion is mounted on the first major surface of the insulating board.

Semiconductor package and method of fabricating a semiconductor package

Growing community of inventors

Torrance, CA, United States of America

Eung San Cho