Samsung Electronics Co., Ltd.

Eunchul Ahn

Jin-Woo Park

Jongho Lee

Young Lyong Kim

Hwan-Sik Lim

Youngmin Lee

Yun-Rae Cho

Choongbin Yim

Taesung Park

Hyeongmun Kang

Cheul-Joong Youn

Hyeongseob Kim

TaeSung Yoon

A semiconductor package, comprising: a semiconductor substrate; a mold layer on the semiconductor substrate; and a marking formed on a surface of the mold layer, the marking comprising dot markings substantially discontinuously arranged in vertical and horizontal directions of a display region. An effective area of the dot markings within a unit display region of the marking is smaller than about half a total area of the unit display region.

Semiconductor package and method of fabricating the same

A semiconductor package and a method for fabricating the same. The semiconductor package includes a first substrate including a first pad, a second substrate spaced apart from the first substrate and where a second pad is formed to face the first pad, a first bump electrically connecting the first pad to the second pad, and a second bump mechanically connecting the first substrate to the second substrate is disposed between the first substrate where the first pad is not formed and the second substrate where the second pad is not formed. A coefficient of thermal expansion (CTE) of the second bump is smaller than that of the first bump.

A package substrate, a semiconductor package having the same, and a method for fabricating the semiconductor package. The semiconductor package includes a semiconductor chip, a package substrate, and a molding layer. The package substrate provides a region mounted with the semiconductor chip. The molding layer is configured to mold the semiconductor chip. The package substrate includes a first opening portion that provides an open region connected electrically to the semiconductor chip and extends beyond sides of the semiconductor chip to be electrically connected to the semiconductor chip.

Package substrates, semiconductor packages having the same, and methods of fabricating the semiconductor packages

A semiconductor package includes a wiring board including an upper connection pad provided on a first surface and a lower connection pad provided on a second surface opposite to the first surface, a semiconductor chip having a bonding pad area in which a bonding pad is provided and an adhesive area except the bonding pad area, and being mounted on the first surface of the wiring board in a flip-chip manner such that the bonding pad is electrically connected to the upper connection pad, a first molding layer provided between the adhesive area of the semiconductor chip and the first surface of the wiring board, and a second molding layer provided between the bonding pad area of the semiconductor chip and the first area of the wiring board while covering the first surface of the wiring board and the semiconductor chip. The first molding layer has a lower modulus than the second molding layer.

Semiconductor packages and methods of fabricating the same

Package substrates and semiconductor packages having the same

Provided is an apparatus for manufacturing a bonding structure, a bonding structure, and a method of fabricating the same. The bonding structure includes a pad including an upper surface with a first area, a ball adhered to the upper surface of the pad, and a wire extending from the ball. An adhesion surface of the ball adhered to the pad may have substantially the same shape as that of the upper surface of the pad.

Apparatus for manufacturing bonding structure, bonding structure and method of fabricating the same

A semiconductor package includes a first package including at least one first semiconductor chip; a second package including an external connection terminal and at least one second semiconductor chip, the second package being stacked on the first package; and an interposer disposed between the first and second packages and connected to the external connection terminal to electrically connect the first and second packages to each other. The interposer comprises an intermediate connector having an exposed end portion to which the second package is electrically connected via the external connection terminal and a protruding end portion lower than the exposed end portion to which the first package is electrically connected.

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Yongin-si, South Korea

Eunchul Ahn