Google Inc.

Eunchan Kim

Timothy Jay Chen

Michael Stefano Fritz Schaffner

Christopher Gori

Scott David Johnson

Miguel Angel Osorio

Ziv Hershman

Mark Hayter

Dominic Rizzo

An IC chip can provide silicon root of trust (RoT) functionality. In described implementations, the IC chip includes a processor, an interconnect, and multiple peripheral devices. These comportable circuit components are designed to facilitate interoperability and consistent, expected communications for security circuitry. Each peripheral device includes an interface that adheres to a common framework for interacting with the processor and with other peripheral devices. The interface includes an interconnect interface coupling the peripheral device to the interconnect and an inter-device interface coupling the peripheral device to at least one other peripheral device. The peripheral device is realized based on a peripheral device design code that indicates inter-device signaling in accordance with an inter-device scheme of an interface specification. Manufacturers fabricate the peripheral device, based on the design code, to be physically and logically coupled to another peripheral device in a predictable manner. This fosters more-robust and reliable security circuitry.

Peripheral device comportability with security circuitry

An IC chip can provide silicon root of trust (RoT) functionality. In described implementations, the IC chip includes a processor, an alert handler, and multiple peripheral devices, which generate alert indications. The alert handler processes the alert indications, which have security implications. The alert handler includes multiple alert receiver modules to communicate with the multiple peripheral devices. The alert handler also includes a controller, multiple accumulation units, multiple escalation timers, and multiple escalation sender modules. These components can be organized into a hierarchy of increasing escalation severity. In operation, the controller classifies an alert and flexibly implements an adaptable alert handler path that is established through the escalation components responsive to the classification and based on a source of the alert. A path can conclude with an escalation sender module commanding an escalation handler to implement a security countermeasure. The flexible paths can therefore handle different types of alerts.

Alert handling

This document includes techniques, apparatuses, and systems related to an interface for revision-limited memory, which can improve various computing aspects and performance. In aspects, confidentiality, integrity, and availability may be ensured while increasing the performance of revision-limited memory. In this example, the techniques also enable the digital computing device to interact with information related to the revision-limited memory.

Interface for revision-limited memory

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San Jose, CA, United States of America

Eunchan Kim