Samsung Electronics Co., Ltd.

Postech Research and Business Development Foundation

Eunae Lee

Jihee Kwak

Kijun Lee

Jihyun Moon

Moonjung Jang

Sunghye Cho

Soyoon Jeon Jeon

Yeonggeol Song

Myungkyu Lee

Jiyun Lim

Junjin Kong

Kyomin Sohn

Jun Jin Kong

Jonghwan Kim

Jeonghan Song

Hayoung Yang

Seijoon Shim

Sungrae Kim

Yesin Ryu

Jihyun Choi

Joonho Cho

Sunggi Ahn

Byeonggyu Park

Seokha Hwang

Taejun Jang

A memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer managing circuit, which is configured to detect a row hammer address based on a pre row hammer address, and each of a plurality of input row addresses associated with a plurality of accesses during a monitoring period for monitoring the plurality of accesses to a plurality of the rows of memory cells. A refresh control circuit is provided and is configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address.

Memory devices and methods thereof for managing row hammer events therein

A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.

Integrated circuit memory devices having efficient row hammer management and memory systems including the same

A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit, and a refresh control circuit. The row hammer management circuit captures row addresses accompanied by first active commands randomly selected from active commands, each of which has a first selection probability that is uniform, from an external memory controller during a reference time interval, and selects at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

Semiconductor memory device and method of operating the same

A memory device includes a memory cell array, an address manager and a refresh controller. The memory cell array includes a plurality of memory cells coupled to a plurality of word-lines. The address manager samples access addresses provided from a memory controller to generate sampling addresses and determines a capture address from among the access addresses, based on a time interval between refresh commands from the memory controller. The refresh controller refreshes target memory cells from among the plurality of memory cells based on one of a maximum access address from among the sampling address and the captured address.

Memory device performing refresh operation and method of operating the same

Wireless communication device

Wireless network device

A memory device includes a memory cell array connected to a plurality of wordlines and a plurality of bitlines; a row decoder configured to select a wordline, among the plurality of wordlines, in response to a row address; a column decoder configured to corresponding bitlines, among the plurality of bitlines, in response to a column address; a sense amplification circuit having a plurality of amplifiers connected to the selected corresponding bitlines; a row hammer detector configured to generate a refresh row address when the number of accesses to a row corresponding to the row address is a multiple of a predetermined value; and a refresh controller configured to perform a refresh operation on a row corresponding to the refresh row address. The row corresponding to the refresh row address is disposed adjacent to the row corresponding to the row address.

Memory device for reducing row hammer disturbance, and a method of refreshing the same

A semiconductor memory device includes a buffer die and a plurality of memory dies. An error correction code (ECC) engine in one of the memory dies performs an RS encoding on a main data to generate a parity data and performs a RS decoding, using a parity check matrix, on the main data and the parity data. The parity check matrix includes sub matrixes and each of the sub matrixes corresponds to two different symbols. Each of the sub matrixes includes two identity sub matrixes and two same alpha matrixes, the two identity sub matrixes are disposed in a first diagonal direction of the sub matrix and the two same alpha matrixes are disposed in a second diagonal direction. A number of high-level value elements in a y-th row of the parity check matrix is the same as a number of high-level value elements in a (y+p)-th row.

Semiconductor memory devices and methods of operating semiconductor memory devices

An error correction device according to the technical idea of the present disclosure includes a syndrome generation circuit configured to receive data and generate a plurality of syndromes for the data, a partial coefficient generation circuit configured to generate partial coefficient information on a part of a coefficient of an error location polynomial by using the data while the plurality of syndromes are generated, an error location determination circuit configured to determine the coefficient of the error location polynomial based on the plurality of syndromes and the partial coefficient information, and obtain a location of an error in the data by using the error location polynomial, and an error correction circuit configured to correct the error in the data according to the location of the error.

Error correction device and method for generating syndromes and partial coefficient information in a parallel

Memory device for reducing row hammer disturbance and a method of refreshing the same

A semiconductor memory device includes a memory cell array, an error correction code (ECC) circuit and a control logic circuit to control the ECC circuit. The memory cell array includes memory cells and a normal cell region and a parity cell region The ECC circuit, in a normal mode, receives a main data, performs an ECC encoding on the main data to generate a parity data and stores the main data and the parity data in the normal cell region and the parity cell region. The ECC circuit, in a test mode, receives a test data including at least one error bit, stores the test data in one of the normal cell region and the parity cell region and performs an ECC decoding on the test data and one of the main data and the parity data to provide a decoding result data to an external device.

Semiconductor memory devices and memory systems including the same

Terminal for networks

Growing community of inventors

Seoul, South Korea

Eunae Lee