Samsung Electronics Co., Ltd.

Eun-young Jin

Dong-hoon Baek

Young-min Choi

Jae-Youl Lee

Hyun-Wook Lim

Kyong-ho Kim

Hyunwook Lim

Kwi-sung Yoo

Kwi Sung Yoo

Seung-hyun Lim

Jaeyoul Lee

Kilhoon Lee

Kwi-Sung Yoo

Won-Ho Choi

Young-Kyun Jeong

Kyo-Jin Choo

Yu-Jin Park

Youngmin Choi

Kyongho Kim

Ji-Hun Shin

Chang-Eun Kang

Han-Kook Cho

Younghwan Chang

Young-Tae Jang

Seng-Sub Chun

Hyuk-Bin Kwon

Dae-Hwa Paik

Kyojin David Choo

Youngseo Kim

An operation method of a receiver, which includes setting a coefficient of an equalizer based on one of a plurality of first codes, setting a coefficient of an amplifier based on one of a plurality of second codes, performing offset calibration by driving the equalizer and the amplifier based on the coefficient of the equalizer and the coefficient of the amplifier, storing an offset code corresponding to a voltage offset generated when the equalizer and the amplifier are driven, determining whether the offset calibration is completed, performing a normal operation of obtaining reception data from an input signal, in response to determining that the offset calibration is completed, and removing the voltage offset based on the offset code, in the normal operation.

Receiver for compensating for voltage offset in real time and operation method thereof

A method of operating a source driver, a display driving circuit, and a method of operating the display driving circuit are provided. The method of operating the source driver including a receiver, includes determining a parameter value of the receiver for optimizing a receiving of the receiver, through training, and transmitting the parameter value to a timing controller external to the source driver. The method of operating the source driver further includes, based on an abnormal state occurring in the receiving of the receiver, receiving the transmitted parameter value from the timing controller, and optimizing the receiving of the receiver based on the received parameter value.

Method of operating source driver, display driving circuit, and method of operating display driving circuit

A method of operating a receiver includes a controller of the receiver determining whether a full initialization or a partial initialization of the receiver is needed; the controller adjusting alternating current (AC) characteristics and direct current (DC) characteristics of the receiver in a full initialization mode, and the controller adjusting the DC characteristics of the receiver in a partial initialization mode when the controller determines the partial initialization is needed.

Operating method of receiver, source driver and display driving circuit including the same

A clock and data recovery circuit in accordance with an embodiment of the inventive concept includes a phase locked loop configured to receive a data stream into which an additional bit is inserted at every reference period to generate parallelized data and a clock signal, and a first detector circuit configured to determine whether the parallelized data is locked based on a bit-conversion of the data stream according to an insertion of the additional bit. The bit-conversion is executed with respect to the additional bits according to a predetermined protocol, or is executed with respect to at least one bit from among data of the data stream between a current one of the additional bits and a next one of the additional bits.

Clock and data recovery circuit detecting unlock of output of phase locked loop

An integrated circuit comprises a first signal transfer block comprising first through (M)-th aligning blocks that are cascade-coupled to produce first aligned control signals through (M)-th aligned control signals, respectively, by aligning first control signals with a clock signal, wherein M is an integer greater than one, and a functional block divided into first through (M)-th sub-functional blocks configured to perform a same function in parallel, each of the first through (M)-th sub-functional blocks operating according to corresponding ones of the first aligned control signals through (M)-th aligned control signals generated by the first through (M)-th aligning blocks.

Integrated circuit and image sensor comprising same

A data transmission circuit includes a data output unit (DOU) connected to a positive data transmission line and a negative data transmission line. The DOU generates a recovered data signal based on data signals communicated via the positive and negative data transmission lines. Data signal driving units are respectively connected at different points along the positive and negative data transmission lines, where each data signal driving unit generates and provides a positive data signal and a negative data signal based on a data input signal and a data transmission distance between the data signal driving unit and the data output unit.

Data transmission circuit, image sensor including the same

An image sensor is provided. The image sensor includes a converter configured to convert a photoelectric converted analog signal in a unit pixel into a digital signal including a plurality of bits, a data transfer unit configured to selectively output the converted digital signal output from the converter in units of bits in response to a control signal, and including a plurality of switching circuits which are serially connected; and a memory configured to store data output from the data transfer unit.

Device and method of transferring sensed data in image sensor

Growing community of inventors

Hwaseong-si, South Korea

Eun-young Jin