Skhynix Inc.

Eun Woo Jo

Jong Woo Kim

Young Ki Kim

Seung Wan Chae

Jong Il Lee

A semiconductor memory device includes a memory cell array including memory cells, a peripheral circuit performing a read/verify operation of selected memory cells, and a control logic circuit controlling the read/verify operation of the peripheral circuit. The control logic circuit controls the peripheral circuit to apply a first voltage to a selected word line connected to the selected memory cells, float unselected word lines adjacent to the selected word line among unselected word lines, apply a first under-drive voltage lower than the first voltage to the selected word line during at least a partial period in which the unselected word lines adjacent to the selected word line are floated, and apply a second voltage higher than the first under-drive voltage and lower than the first voltage to the selected word line.

Semiconductor memory device and method of operating the same

A semiconductor memory device includes a memory cell array, a row decoder, a plurality of page buffers, and a voltage switching circuit. The memory cell array includes a plurality of memory cells. The row decoder is connected to the memory cell array through word lines. The plurality of page buffers are connected to the memory cell array through bit lines. The voltage switching circuit decodes an operation voltage and transmits the decoded operation voltage to the row decoder. The plurality of page buffers are formed in a first under cell region among first and second under cell regions, the first and second under cell regions being adjacent to each other in a first direction under the memory cell array. At least a portion of the voltage switching circuit is formed in an under slim region that is adjacent to the first under cell region and the second under cell region in a second direction.

Growing community of inventors

Icheon-si, South Korea

Eun Woo Jo