Electronics and Telecommunications Research Institute

Eun Tae Kim

Hee Sang Chung

Gweon Do Jo

Hyeong Jun Park

Hyung Jung Kim

Dae Soon Cho

Bong Guk Yu

The present invention relates to an apparatus for generating a clock signal with jitter and a test apparatus including the same. The apparatus for generating a clock signal with jitter in accordance with the present invention includes a voltage-controlled crystal oscillator (VCXO) for generating an output signal including jitter components based on a driving power source having a specific waveform and a controlled voltage, a phase comparator for calculating a phase difference of a reference signal and the output signal, and a loop filter for generating the controlled voltage based on the phase difference calculated by the phase comparator. Accordingly, the PLL circuit unit generates a clock signal including jitter, so that the complexity and manufacturing cost of the apparatus can be reduced.

Apparatus for generating clock signal with jitter and test apparatus including the same

Provided are a method and apparatus for derate matching a rate-matched data. The received data is deinterleaved and derate matched at a time, without using input buffers or constructing input buffers in parallel. Thus, a total process time necessary for the deinterleaving process and the derate matching process is reduced, and the use of memories such as the input buffers is minimized.

Derate matching method and apparatus

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Daejeon, South Korea

Eun Tae Kim