Samsung Electronics Co., Ltd.

Eun-Sun Lee

Ji Hun Kim

Jeonghoon Oh

Junhwa Song

Ilgweon Kim

Young-Min Kang

WonSeok Yoo

A method of fabricating a semiconductor device, the method including etching a portion of a substrate including a first region and a second region to form a device isolation trench; forming a device isolation layer defining active regions by sequentially stacking a first insulating layer, a second insulating layer, and a third insulating layer on an inner surface of the device isolation trench; forming word lines buried in the substrate of the first region, the word lines extending in a first direction to intersect the active region of the first region, the word lines being spaced apart from each other; forming a first mask layer covering the word lines on the substrate of the first region, the first mask layer exposing the substrate of the second region; forming a channel layer on the substrate of the second region; and forming a gate electrode on the channel layer.

Semiconductor device and method of fabricating the same

A semiconductor device includes a semiconductor substrate including a well dopant layer having a first conductivity type, a gate electrode on the well dopant layer, a channel dopant layer in the well dopant layer and spaced apart from a top surface of the semiconductor substrate, a channel region between the gate electrode and the channel dopant layer, and source/drain regions in the well dopant layer at both sides of the gate electrode. The channel dopant layer and the channel region have the first conductivity type. The source/drain regions have a second conductivity type. A concentration of dopants having the first conductivity type in the channel dopant layer is higher than a concentration of dopants having the first conductivity type in the channel region. The semiconductor device may be used in a sense amplifier of a memory device.

Semiconductor devices including channel dopant layer

An FRAM device includes first ferroelectric capacitors, second ferroelectric capacitors, first plate lines and second plate lines. The first ferroelectric capacitors can be connected between word lines and bit lines. The second ferroelectric capacitors can be connected between the word lines and bit line bars. The first plate lines can be connected to upper electrodes of the first ferroelectric capacitors. The second plate lines can be connected to upper electrodes of the second ferroelectric capacitors. Thus, the first ferroelectric capacitors connected to the bit lines and the second ferroelectric capacitors connected to the bit line bars can be connected to the different plate lines, so that data can be output from any one of the bit line and the bit line bar. As a result, a layout of a core region can be simplified.

Growing community of inventors

Yongin-si, South Korea

Eun-Sun Lee