Hynix Semiconductor Inc.

Sanken Electric Co., Ltd.

Sanken Electric Korea Co., Ltd.

Eun Suk Lee

Masaaki Shimada

Hiroaki Nakamura

Tetsuya Tabata

Mi Yong Kim

Jung Eun Oh

A device and method for controlling a power supply. The method includes: a first correction signal is generated according to a down-slope waveform and a second correction signal is generated according to an up-slope waveform, in a period of the switching element. Therefore, two kinds of corrections can be performed by using an oscillator, while the area of the circuit can be reduced and the cost of the integrated circuit can be decreased.

Device and method for controlling power supply with correction behaviour in a power circuit

A device and method for controlling a power supply. The method includes: monitoring a feedback signal of a feedback terminal; determining whether the feedback signal of the feedback terminal is not a pulse signal; and terminating an on/off operation of a switching element when the feedback signal of the feedback terminal is not a pulse signal. Therefore, an abnormal status of the device can be correctly detected with a simple structure when the feedback terminal is open or is shorted with other terminals, while an error operation and a damage of the device can be avoided.

Device and method for controlling power supply

A MOSFET device includes a semiconductor substrate having an active region including storage node contact forming areas and a device isolation region and having a device isolation structure which is formed in the device isolation region to delimit the active region; screening layers formed in portions of the device isolation structure on both sides of the storage node contact forming areas of the active region; a gate line including a main gate which is located in the active region and a passing gate which is located on the device isolation structure; and junction areas formed in a surface of the active region on both sides of the main gate.

MOSFET device having screening layers formed between main gate and passing gate and method for manufacturing the same

Disclosed is a memory device, which combines a self-refresh enable signal and a power mode decision signal and prevents an internal voltage from being dropped down without the increase of IDD3P current when the memory device performs a self-refresh operation. The memory device includes an operation mode internal voltage generator used in an operation mode, and a controller for enabling the operation mode internal voltage generator while performing a self-refresh operation with a predetermined period and activating a memory cell array of the memory device, even when the memory device is in a stand-by mode.

Dual operation mode memory device

Disclosed are a chain gate line structure of a semiconductor device, and a method for manufacturing the same. The semiconductor device having a gate line structure comprises device isolation films formed on a semiconductor substrate for defining active regions and inactive regions; stack type gate electrodes formed on top of the active regions of the semiconductor substrate; at least one layer of an interlayer insulating film formed on the entire surface of the resultant material having the stack type gate electrodes; gate contacts formed on contact holes of the interlayer insulating film and connected to the stack type gate electrodes; and chain type gate lines for connecting the gate contacts formed in the active regions arrayed in a row among a plurality of active regions on the top of the interlayer insulating film in a concave-convex type chain structure. The chain gate line structure can enlarge active regions of a cell in a longitudinal axis direction by changing gate lines of the cell from a serial array into a chain line structure by having stack type gate electrodes and chain type gate lines connected thereto, and accordingly can reduce the contact resistance of the cell.

Growing community of inventors

Seoul, South Korea

Eun Suk Lee