Hewlett Packard Enterprise Development LP

Eun Sub Lee

Martin Foltin

Craig William Warner

Sai Rahul Chalamalasetti

Arthur Carvalho Walraven Da Cunha

Lucas Leite

Rodrigo Jose Da Rosa Antunes

Monycky Vasconcelos Frazao

Francisco Plínio Oliveira Silveira

Alex Ferreira Ramires Trajano

Joaquim Gomes Da Costa Eulalio De Souza

Glaucimar Da Silva Aguiar

Jefferson Rodrigo Alves Cavalcante

Systems and methods are provided to improve traditional chip processing. Using crossbar computations, the convolution layer can be flattened into vectors, and the vectors can be grouped into a matrix where each row or column is a flattened filter. Each submatrix of the input corresponding to a position of a convolution window is also flattened into a vector. The convolution is computed as the dot product of each input vector and the filter matrix. Using intra-crossbar computations, the unused space of the crossbars is used to store replicas of the filters matrices and the unused space in XIN is used to store more elements of the input. In inter-crossbar computations, the unused crossbars are used to store replicas of the filters matrices and the unused XINs are used to store more elements of the input. Then, the method performs multiple convolution iterations in a single step.

System and method for processing convolutions on crossbar-based neural network accelerators for increased inference throughput

Systems and methods are provided for a multi-die dot-product engine (DPE) to provision large-scale machine learning inference applications. The multi-die DPE leverages a multi-chip architecture. For example, a multi-chip interface can include a plurality of DPE chips, where each DPE chip performs inference computations for performing deep learning operations. A hardware interface between a memory of a host computer and the plurality of DPE chips communicatively connects the plurality of DPE chips to the memory of the host computer system during an inference operation such that the deep learning operations are spanned across the plurality of DPE chips. Due to the multi-die architecture, multiple silicon devices are allowed to be used for inference, thereby enabling power-efficient inference for large-scale machine learning applications and complex deep neural networks. The multi-die DPE can be used to build a multi-device DNN inference system performing specific applications, such as object recognition, with high accuracy.

Multi-die dot-product engine to provision large scale machine learning inference applications

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Plano, TX, United States of America

Eun Sub Lee