Skhynix Inc.

Eun-Soo Jang

Jin-Woong Kim

Hae-Gi Choi

Kyeong-Rho Kim

Hui-Won Lee

Su-Chang Kim

A method for operating a data processing system including a host and a memory system coupled to each other through a plurality of slots and using a Universal Flash Storage (UFS) interface, the method includes: allocating, by the host, dedicated memory regions respectively corresponding to the slots during a booting operation of the host; communicating, between the host and the memory system in parallel through the slots based on command packets and address information for data buffer regions, the command packets and the address information being stored in the dedicated memory regions; and deallocating, by the host, the dedicated memory regions during a shutdown of the host.

Data processing system and operating method thereof

A memory system includes a nonvolatile memory device including a plurality of memory blocks each including a plurality of pages; and a controller suitable for, when writing a plurality of data in the pages according to a write request from a host, writing the plurality of data with tags, classified into N number of kinds depending on a usage pattern of each data, together in the pages. The controller manages a list of victim blocks as a target of a merge operation, the controller manages entire valid pages included in the victim blocks, by classifying them into N number of page groups depending on a kind of each of the entire valid pages, and the controller selects valid pages to be moved to a free block in the merge operation, among the entire valid pages, and N may be a natural number of 2 or greater.

Memory system and operating method thereof

A controller includes: a counter suitable for counting a number of valid pages in each of a plurality of blocks in a memory device as first parameter values; a block selector suitable for selecting one or more first candidate blocks, the first parameter value of each of which is within a predetermined range, and selecting a victim block among the one or more first candidate blocks; and a processor suitable for controlling the memory device to read valid data stored in the victim block and program the valid data into a target block in the memory device.

Controller and operating method thereof

A memory system may include: a first memory device including a first normal block and a first auxiliary block; a second memory device including a second normal block and a second auxiliary block; and a controller configured to operate the first and second memory devices in an interleaving scheme, wherein the controller: checks a first used area of a cache buffer when a first data is buffered which is the most recently inputted, programs the first data in the first or second auxiliary block without erasing the first data from the cache buffer, when the first used area of the cache buffer is smaller than a predetermined size, and programs a second data of the predetermined size, which occupies a part of the first used area of the cache buffer, to the first or second normal block with erasing the second data from the cache buffer, when the first used area of the cache buffer is equal to or larger than the predetermined size.

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Gyeonggi-do, South Korea

Eun-Soo Jang