Samsung Electro-mechanics Co., Ltd.

Samsung Electronics Co., Ltd.

Eun Sil Kim

Yeong A Kim

Jun Woo Myung

Akihisa Kuroyanagi

Jae Hoon Choi

Bae Kyun Kim

Se Woong Paeng

Jin Su Kim

Yong Il Kwon

Young Gwan Ko

Sung Han Kim

Doo Hwan Lee

Sang Hyun Shin

Dae Jung Byun

Sa Yong Lee

Jin Ho Hong

Tae Ho Ko

Keun Yong Lee

Ji Sung Cho

A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip disposed in the recess portion; a resin layer disposed on an active surface of the semiconductor chip; an encapsulant covering at least portions of side surfaces of the semiconductor chip and the resin layer and filling at least portions of the recess portion; a first redistribution layer disposed on the resin layer and the encapsulant; first redistribution vias penetrating through the resin layer to fill via holes in the resin layer exposing at least portions of the connection pads and electrically connecting the connection pads and the first redistribution layer to each other; and a connection member disposed on the resin layer and the encapsulant and including one or more second redistribution layers.

Fan-out semiconductor package

A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed on side surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.

Semiconductor package including organic interposer

A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed onside surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.

A fan-out semiconductor package module includes a core member having first and second through-holes. A semiconductor chip is in the first through-hole and has an active surface with a connection pad and an inactive surface opposing the active surface. Another passive component is in the second through-hole. An first encapsulant covers at least portions of the core member and the passive component, and fills at least a portion of the second through-hole. A reinforcing member is on the first encapsulant. A second encapsulant covers at least a portion of the semiconductor chip, and fills at least a portion of the first through-hole. A connection member is on the core member, the active surface of the semiconductor chip, and the passive component, and includes a redistribution layer electrically connected to the connection pad and the passive component.

Fan-out semiconductor package module

A fan-out semiconductor package includes: a fan-out semiconductor package may include: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first interconnection member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a reinforcing layer disposed on the encapsulant. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to the connection pads of the semiconductor chip.

Disclosed herein are a printed circuit board and a method of manufacturing the same. The printed circuit board includes a light-blocking glass substrate; a negative photosensitive insulating layer formed on the glass substrate; and a circuit pattern formed on the glass substrate and embedded in the negative photosensitive insulating layer.

Printed circuit board and method of manufacturing the same

Disclosed herein is an apparatus for storing an electric energy, the apparatus including: an electrode stack in which a cathode and an anode in which a cathode lead and an anode lead are respectively formed are alternately stacked; and collector plates disposed at both sides of the electrode stack, connected to the cathode lead and the anode lead, and provided with external terminals and one or more electrolyte flow holes.

Apparatus for storing electric energy and method of manufacturing the same

The present invention relates to an electrolyte of an energy storage device. An electrolyte composition in accordance with an embodiment of the present invention includes an electrolyte salt, a carbonate solvent, and at least one nitrile solvent of acetonitrile and propionitrile.

Growing community of inventors

Suwon-si, South Korea

Eun Sil Kim