Samsung Electronics Co., Ltd.

Eun-Ok Lee

Hyun-Su Kim

Byung-Hee Kim

Dae-Yong Kim

Gil-heyun Choi

Sang-Woo Lee

Nam-Gun Kim

Eun-Ji Jung

Hyun-jung Lee

Kwang-jin Moon

Gyuhwan Oh

Heesook Park

Ho-Ki Lee

Kyungho Jang

Kwang-Jin Moon

Jang-Hee Lee

Min-sang Song

Jong-Ho Yun

Woong-hee Sohn

Young-Mo Gu

Jong-ho Yun

Eun-ji Jung

Dae-yong Kim

Sung-Tae Kim

Sang-Hyo Kim

Han-Ju Kim

Taek Jung Kim

Hyun Su Kim

Sun Yong Hwang

Hyun-soo Kim

Hyo Jung Noh

Ji Won Yu

A deposition equipment is provided. The deposition equipment includes: a reaction chamber including an upper plate and a container body, the upper plate including a gas supplier for injecting a processing gas; a wafer chuck including an upper surface on which a wafer is loaded, in the reaction chamber, with the upper surface of the wafer chuck facing the upper plate; and a processing gas shielding section which prevents the processing gas from being adsorbed to the upper surface of the wafer chuck and is disposed between the upper plate and the wafer chuck in a state in which the wafer is removed from the wafer chuck. The processing gas shielding section includes a shutter which is plate-like, and the shutter includes a region including a gas discharge section for jetting a purging gas toward the wafer chuck.

Deposition equipment and method of fabricating semiconductor device using the same

A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of the first and second portions of the spacer is spaced apart from a metal silicide layer of the contact plug. Thus reliability of the semiconductor device may be improved. Related fabrication methods are also described.

Semiconductor devices including spacers

Methods of manufacturing semiconductor devices including air gap spacers

Semiconductor devices including air gap spacers

A semiconductor memory wiring method includes: receiving a substrate having a cell array region and a peripheral circuit region; depositing a first insulating layer on the substrate; forming a first contact plug in the cell array region, the first contact plug having a first conductive material extending through the first insulating layer; forming a first elongated conductive line at substantially the same time as forming the first contact plug, the first elongated conductive line having the first conductive material directly covering and integrated with the first contact plug; forming a second contact plug in the peripheral circuit region at substantially the same time as forming the first contact plug, the second contact plug having the first conductive material extending through the first insulating layer; and forming a second elongated conductive line at substantially the same time as forming the second contact plug, the second elongated conductive line having the first conductive material directly covering and integrated with the second contact plug.

Methods of forming wiring structures

A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other.

Semiconductor device and method of manufacturing the same

Contacts having different characteristics may be created by forming a first silicide layer over a first device region of a substrate, and then forming a second silicide layer over a second device region while simultaneously further forming the first silicide layer. A first contact hole may be formed in a dielectric layer over a first device region of a substrate. A silicide layer may then be formed in the first contact hole. A second contact hole may be formed after the first contact hole and silicide layer is formed. A second silicidation may then be performed in the first and second contact holes.

Method for forming silicide contacts

A method of forming a buried gate electrode prevents voids from being formed in a silicide layer of the gate electrode. The method begins by forming a trench in a semiconductor substrate, forming a conformal gate oxide layer on the semiconductor in which the trench has been formed, forming a first gate electrode layer on the gate oxide layer, forming a silicon layer on the first gate electrode layer to fill the trench. Then, a portion of the first gate electrode layer is removed to form a recess which exposed a portion of a lateral surface of the silicon layer. A metal layer is then formed on the semiconductor substrate including on the silicon layer. Next, the semiconductor substrate is annealed while the lateral surface of the silicon layer is exposed to form a metal silicide layer on the silicon layer.

Method of forming buried gate electrode utilizing formation of conformal gate oxide and gate electrode layers

A method of forming an ohmic contact layer including forming an insulation layer pattern on a substrate, the insulation pattern layer having an opening selectively exposing a silicon bearing layer, forming a metal layer on the exposed silicon bearing layer using an electrode-less plating process, and forming a metal silicide layer from the silicon bearing layer and the metal layer using a silicidation process. Also, a method of forming metal wiring in a semiconductor device using the foregoing method of forming an ohmic contact layer.

Method forming ohmic contact layer and metal wiring in semiconductor device

A semiconductor device includes a plurality of channel structures on a semiconductor substrate. A bit line groove having opposing sidewalls is defined between sidewalls of adjacent ones of the plurality of channel structures. A plurality of bit lines are formed on corresponding ones of the opposing sidewalls, and the plurality of bit lines are electrically isolated from each other

Semiconductor devices including buried bit lines

A method and apparatus for decoding a concatenated burst in a WiBro system are provided. A concatenated decoder fragments a received burst into fragment blocks, decodes at least one of the fragment blocks, and determines whether the decoded fragment block satisfies a circular state. A concatenated decoding controller determines burst quality information of the received burst according to a circular state check result on the decoded fragment block, and determines whether to stop decoding on the received burst according to the burst quality information.

Method and apparatus for efficiently decoding concatenated burst in a WiBro system

A method of forming a buried interconnection includes removing a semiconductor substrate to form a groove in the semiconductor substrate. A metal layer is formed on inner walls of the groove using an electroless deposition technique. A silicidation process is applied to the substrate having the metal layer, thereby forming a metal silicide layer on the inner walls of the groove.

Methods of forming a semiconductor device including buried bit line

A method of fabricating a semiconductor device includes forming a preliminary gate pattern on a semiconductor substrate. The preliminary gate pattern includes a gate oxide pattern, a conductive pattern, and a sacrificial insulating pattern. The method further includes forming spacers on opposite sidewalls of the preliminary gate pattern, forming an interlayer dielectric pattern to expose the sacrificial insulating pattern, removing the sacrificial insulating pattern to form an opening to expose the conductive pattern, transforming the conductive pattern into a metal silicide layer and forming a metal barrier pattern along an inner profile of the opening and a metal conductive pattern to fill the opening including the metal barrier pattern. The metal silicide layer and the metal conductive pattern constitute a gate electrode.

Semiconductor device and method of fabricating the same

A method of manufacturing a semiconductor device includes forming a pillar-shaped active region by etching a portion of a semiconductor substrate, forming a blocking film selectively exposing a sidewall of a lower portion of the pillar-shaped active region, and forming a bit-line selectively on the exposed sidewall of the lower portion of the pillar-shaped active region.

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Hwaseong-si, South Korea

Eun-Ok Lee