Samsung Electronics Co., Ltd.

Eun-Chul Ahn

Tae-Gyeong Chung

Tae-Joo Hwang

Pyoung-Wan Kim

Jong-Ho Lee

Hyun-Soo Chung

Sang-Young Kim

Jin-ho Chun

Chang-Woo Shin

Chul-yong Jang

Moon-Gi Cho

Jum-Gon Kim

Min-Ho Lee

Min-Ho O

Joo-Weon Shin

Jin-Woo Park

Jong Ho Lee

Nam-seog Kim

Sun-Won Kang

Teak-Hoon Lee

Chul-Yong Jang

Dong-Kil Shin

Hee-Jin Park

Teak-hoon Lee

Hae-jung Yu

Young-Lyong Kim

Byung-Woo Lee

Taek-Hoon Lee

A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal.

Semiconductor package and method of forming the same

A semiconductor device has improved reliability by preventing a fuse cut through a repair process from being electrically reconnected by electrochemical migration. The semiconductor device includes a substrate, a fuse including a first fuse pattern and a second fuse pattern formed at the same level on the substrate, the first fuse pattern and the second fuse pattern being spaced a first width apart from each other such that a gap in the fuse is disposed at a first location between the first fuse pattern and the second fuse pattern, and a first insulation layer formed on the first fuse pattern and the second fuse pattern, the first insulation layer including an opening above the first location and having a second width smaller than the first width.

Semiconductor device having fuse pattern

In an integrated circuit (IC) chip and a flip chip package having the same, no wiring line is provided and the first electrode pad does not make contact with the wiring line in a pad area of the IC chip. Thus, the first bump structure makes contact with the first electrode regardless of the wiring line in the pad area. The second electrode pad makes contact with the wiring line in a pseudo pad area of the IC chip. Thus, the second bump structure in the pseudo pad area makes contact with an upper surface of the second electrode at a contact point(s) spaced apart from the wiring line under the second electrode.

Integrated circuit chip and flip chip package having the integrated circuit chip

A semiconductor device including an interconnection structure including a copper pad, a pad barrier layer and a metal redistribution layer, an interconnection structure thereof and methods of fabricating the same are provided. The semiconductor device includes a copper pad disposed on a first layer, a pad barrier layer including titanium disposed on the copper pad, an inorganic insulating layer disposed on the pad barrier layer, a buffer layer disposed on the inorganic insulating layer, wherein the inorganic insulating layer and the buffer layer expose a portion of the pad barrier layer, a seed metal layer disposed on the exposed buffer layer, a metal redistribution layer disposed on the seed metal layer, and a first protective layer disposed on the metal redistribution layer.

Inter connection structure including copper pad and pad barrier layer, semiconductor device and electronic apparatus including the same

A stacked semiconductor package includes an upper unit package and a lower unit package. The lower unit package includes a substrate, a semiconductor chip disposed on an upper surface of the substrate, terminal pads arranged on an upper surface of the semiconductor chip, protrusions formed on the terminal pads, a protective layer formed on the substrate and covering the semiconductor chip and the protrusions, and openings formed in the protective layer and exposing the protrusions. The upper unit package includes a substrate, ball lands provided on a lower surface of the substrate, and solder balls formed on the ball lands. The solder balls of the upper unit package are inserted into the openings of the lower unit package to be connected to the protrusions of the lower unit package.

Stacked semiconductor package having reduced height

A semiconductor package may include a semiconductor chip, a molding layer which molds the semiconductor chip, and an interconnection which extends crossing an interface between the semiconductor chip and the molding layer and connects the semiconductor chip to an outside, wherein a shape of the interconnection is changed along the extended length thereof. According to the present invention, even if a mechanical stress or a thermal stress is applied to an interconnection, a crack does not occur in the interconnection or the interconnection is not disconnected. Therefore, a reliability of the semiconductor package is improved.

Semiconductor package and electronic device having the same

Example embodiments relate to semiconductor packages and methods of forming the same. A semiconductor package according to example embodiments may include a printed circuit board (PCB), a first semiconductor chip mounted on the PCB, and a chip package mounted on the first semiconductor chip. The chip package may be in direct contact with the first semiconductor chip.

A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.

Semiconductor chip package, electronic device including the semiconductor chip package and methods of fabricating the electronic device

A method of fabricating an electronic device having stacked chips is provided. The method includes forming a plurality of chips arranged in a row direction and at least one chip arranged in a column direction. A molding layer is formed between the chips. Grooves are formed in the molding layer between the chips arranged in the row direction. Conductive interconnections are formed on the substrate having the grooves. The substrate is sawn along an odd- or even-numbered one of the grooves to be separated into a plurality of unit substrates. At least one of the separated unit substrates is folded along an unsawn groove of the grooves.

Method of fabricating electronic device having stacked chips

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Yongin-si, South Korea

Eun-Chul Ahn