Samsung Electronics Co., Ltd.

Eun-Cheol Kim

Yeong-taek Lee

Jong-Hwa Kim

Hee-Choul Park

Chul-Min Jung

Kook-Hwan Kwon

A non-volatile semiconductor memory device including a memory cell array having a plurality of memory cells coupled to a plurality of bitlines and wordlines, each memory cell being programmed to one of plurality of data storage states. A node is connected to a selected bitline responsive to a storage state in a selected memory cell. A plurality of latched registers is connected to the node to store and output data bits corresponding the storage state, the data bits being assigned to the selected bitline. A circuit is adapted to precharge the selected bitline before sensing the selected memory cell and is adapted to equalize the selected bitline and the node after sensing the selected memory cell.

Multi-state non-volatile semiconductor memory device

A burst-type random access memory device according to the present invention includes an address generator that receives an initial address to generate a sequence of burst addresses according to either one of a single data rate mode and a double data rate mode. A decoding circuit decodes the burst address thus generated. Therefore, in the memory device are automatically generated a sequence of burst addresses necessary for a sequential/interleaved burst operation of the single data rate mode and the double data rate mode.

Address generating and decoding circuit for use in a burst-type and high-speed random access memory device which has a single data rate and a double data rate scheme

The method for programming a flash memory device includes sequentially loading program data in the page buffer circuit responsive to a first command signal, the first command signal indicating program data input and generating a program voltage responsive to a second command signal, the second command signal indicating programming initiation. EEPROM cells are programmed after the program voltage reaches a predetermined target. All of the programmed EEPROM cells are verified to ensure that they are properly programmed. If the EEPROM cells are not properly programmed, programming is repeated until all of the EEPROM cells are properly programmed. The program voltage is increased in a stepwise manner every time programming is repeated.

Method for programming a flash memory device

A clock monitor circuit includes a first and second delay and clock signal generating unit for receiving a clock signal and an inverted clock signal, respectively. The first and second delay and clock signal generating units generate a first and second signals, respectively. A logic sum unit logically-sums the first and second signals to generate a stop clock signal. The clock monitor circuit according to the present invention can monitor the presence of a clock signal irrespective of an operation cycle of the clock signal. Further, the synchronous semiconductor memory device utilizing the clock monitor circuit according to the present invention is adapted to consume electric current only when a clock signal is present. That is, the device does not consume electric current when the clock signal is not present thereby reducing unnecessary waste of electric power in the stand-by mode.

Clock monitor circuit and synchronous semiconductor memory device utilizing the circuit

A burst SRAM device is provided having a burst column selection circuit which is activated in accordance with a burst address, in addition to a column selection circuit for selecting columns of a memory cell array capable of storing a binary data. An internal column address portion of an external column address is applied to the column selection circuit as a first burst address signal. The column selection circuit selects at the same time at least two columns in response to the first burst address signal. During a burst read mode, at least two columns are simultaneously selected in response to the first burst address signal, and data stored in the selected cells are simultaneously sensed and amplified by at least two sense amplifiers corresponding to the selected memory cells. The data amplified thus are stored in a data output register. The burst addresses are applied to the burst column selection circuit. The burst column selection circuit allows the data stored in the data output register to be sequentially delivered to input/output data line pair in response to the burst addresses. As a result, an interval between a generation time of the first burst address and the time, which takes for a sensing operation of the last 1-bit data to be completed by the last burst address, can be considerably shortened as compared with the conventional device. During a burst write mode, at least two columns are simultaneously selected by the first burst address, and 1-bit data from the input/output data line pair corresponding to locations of the first burst address of the data input register are stored. The burst column selection circuit allows the data delivered sequentially from the data line pair to be sequentially stored in regions of the other burst addresses of the data input register in response to the other burst addresses. At least 2-bit data stored in the data input register are sequentially or simultaneously written in the selected memory cells of the selected columns.

Random access memory having burst mode capability and method for

A semiconductor memory device for providing a burst mode control signal. The semiconductor memory device includes a first logic circuit for generating a driving signal in response to a first logic level of an externally input write and read control signal and an externally input chip enable signal, a plurality of transition registers for respectively changing the driving signal in synchronization with a first edge of a clock signal to generate changed driving signals, and a second logic circuit for generating the burst mode control signal generated by the logic combination of the changed driving signals in response to a read latency control signal.

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Kyunggi-do, South Korea

Eun-Cheol Kim