Samsung Electronics Co., Ltd.

Eun-ae Chung

Young-sun Kim

Cha-young Yoo

Jong-Cheol Lee

Hoon-Sang Choi

Doo-sup Hwang

Ki-Vin Im

Myoung-Bum Lee

Young-Pil Kim

Gab-Jin Nam

Sang-yeol Kang

Jin-Gyun Kim

Sang-Yeol Kang

Ji-Young Min

Bean-Jun Jin

Seok-Jun Won

Dong-Chan Kim

Jae-hyoung Choi

Yong-Kuk Jeong

Sung-Il Cho

Jung-dal Choi

Wan-don Kim

Chang-Jin Kang

Cha-Young Yoo

Yun-Jung Lee

Beom-jun Jin

Jae-Hyun Yeo

Byeong-Yun Nam

Jung-hee Chung

Kwang-Hee Lee

U-in Chung

Toshiro Nakanishi

Wan-Don Kim

Ki-hyun Hwang

Jung-Hwan Oh

Jae-Hyun Joo

Sung-Kweon Baek

Dong-kyu Lee

Hee-Seok Kim

Ki-Sun Kim

Jin-Tae Noh

Jong-cheol Lee

Seok-woo Nam

Won-sik Shin

Hyo-jung Kim

Soon-yeon Park

Guangfan Jiao

Hee-don Hwang

Jae-hyun Yeo

Jin-Soak Kim

Ki-vin Lim

Ki-Vin Lim

Hoon-sang Choi

Kyeong-Koo Ghi

Yu-bin Kim

Beom-jun Jim

A semiconductor device includes a substrate having a logic device region including logic devices thereon, and an input/output (I/O) device region including I/O devices thereon adjacent the logic device region. A first fin field-effect transistor (FinFET) on the logic device region includes a first semiconductor fin protruding from the substrate, and a triple-gate structure having a first gate dielectric layer and a first gate electrode thereon. A second FinFET on the I/O device region includes a second semiconductor fin protruding from the substrate, and a double-gate structure having a second gate dielectric layer and a second gate electrode thereon. The first and second gate dielectric layers have different thicknesses. Related devices and fabrication methods are also discussed.

Semiconductor device including FinFETs having different gate structures and method of manufacturing the semiconductor device

A semiconductor device includes a first source/drain region and a second source/drain region disposed in an active region of a semiconductor substrate, and a gate structure crossing the active region and disposed between the first and second source/drain regions, the gate structure including a gate electrode having a first part and a second part on the first part, the gate electrode being at a lower level than an upper surface of the active region, an insulating capping pattern on the gate electrode, a gate dielectric between the gate electrode and the active region, and an empty space between the active region and the second part of the gate electrode.

Semiconductor device and semiconductor module

A method according to example embodiments includes forming isolation regions in a substrate, the isolation regions defining active regions. Desired regions of the active regions and the isolation regions are removed, thereby forming recess channel trenches to a desired depth. The recess channel trenches are fog to have a first region in contact with the active regions and a second region in contact with the isolation regions. A width of a bottom surface of the recess channel trenches is less than that of a top surface thereof. The active regions and the isolation regions are annealed to uplift the bottom surface of the recess channel trenches. An area of the bottom surface of the first region is increased. A depth of the bottom surface of the first region is reduced.

Methods of manufacturing semiconductor devices having a recessed-channel

A semiconductor device including a multilayer dielectric film and a method for fabricating the semiconductor device are disclosed. The multilayer dielectric film includes a type-one dielectric film having a tetragonal crystalline structure, wherein the type-one dielectric film comprises a first substance. The multilayer dielectric film also comprises a type-two dielectric film also having a tetragonal crystalline structure, wherein the type-two dielectric film comprises a second substance different from the first substance and a dielectric constant of the type-two dielectric film is greater than a dielectric constant of the type-one dielectric film.

Semiconductor device comprising multilayer dielectric film and related method

A multi-dielectric film including at least one first dielectric film that is a composite film made of zirconium-hafnium-oxide and at least one second dielectric film that is a metal oxide film made of amorphous metal oxide. Adjacent ones of the dielectric films are made of different materials.

Multi-dielectric films for semiconductor devices and methods of fabricating multi-dielectric films

Provided is an in-situ method of cleaning a vaporizer of an atomic layer deposition apparatus during a dielectric layer deposition process, to prevent nozzle blocking in the vaporizer and an atomic layer deposition apparatus. During the dielectric layer deposition process, the following steps are repeated: supplying a first source gas for dielectric layer deposition into a chamber of an atomic layer deposition apparatus; purging the first source gas; supplying a second source gas into the chamber of the atomic layer deposition apparatus; purging the second source gas, the in-situ method of cleaning the vaporizer is performed after supplying the first source gas for dielectric layer deposition and before supplying the first source gas again.

In-situ method of cleaning vaporizer during dielectric layer deposition process

A method of forming a semiconductor device includes loading a semiconductor substrate into a reaction chamber, and providing metal organic precursors including hafnium and zirconium into the reaction chamber to form hafnium-zirconium oxide (HfZrO; 0&#x3c;X&#x3c;1) with a tetragonal crystalline structure on the semiconductor substrate. Related structures are also discussed.

Semiconductor devices having dielectric layers and methods of forming the same

A method of forming a dielectric layer in a capacitor adapted for use in a semiconductor device is disclosed. The method includes forming a first ZrOlayer, forming an interfacial layer using a plasma treatment on the first ZrOlayer, and forming a second ZrOlayer on the interfacial layer.

Method manufacturing capacitor dielectric

A semiconductor device includes a lower electrode of a capacitor, a dielectric layer disposed on the lower electrode, and an upper electrode of the capacitor disposed on the dielectric layer. The upper electrode includes a doped poly-SiGelayer. An interlayer insulating layer is disposed on the doped poly-SiGelayer and has a contact hole partially exposing the doped poly-SiGelayer. A metal contact plug is in the contact hole and an interconnection layer is disposed on the interlayer insulating layer and connected to the metal contact plug. Related interconnection structures and fabrication methods are also disclosed.

Semiconductor interconnection structures and capacitors including poly-SiGe layers and metal contact plugs

A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.

Methods of fabricating metal-insulator-metal capacitors with a chemical barrier layer in a lower electrode

Methods of forming capacitor structures may include forming an insulating layer on a substrate, forming a first capacitor electrode on the insulating layer, forming a capacitor dielectric layer on portions of the first capacitor electrode, and forming a second capacitor electrode on the capacitor dielectric layer such that the capacitor dielectric layer is between the first and second capacitor electrodes. More particularly, the first capacitor electrode may define a cavity therein wherein the cavity has a first portion parallel with respect to the substrate and a second portion perpendicular with respect to the substrate. Related structures are also discussed.

Methods of forming capacitor structures including L-shaped cavities

Forming a semiconductor device can include forming an insulating layer on a semiconductor substrate including a conductive region thereof, wherein the insulating layer has a contact hole therein exposing a portion of the conductive region. A polysilicon contact plug can be formed in the contact hole wherein at least a portion of the polysilicon contact plug is doped with an element having a diffusion coeffient that is less than a diffusion coefficient of phosphorus (P). Related structures are also discussed.

Semiconductor devices having contact plugs including polysilicon doped with an impurity having a lesser diffusion coefficient than phosphorus

A capacitor of a semiconductor device includes a cylinder type capacitor lower electrode, a dielectric layer, and an upper electrode. The upper electrode includes a metallic layer on the dielectric layer and a doped polySiGelayer stacked on the metallic layer. Methods of forming these capacitors also are provided.

Methods of forming capacitors of semiconductor devices including silicon-germanium and metallic electrodes

Methods for fabricating a contact of a semiconductor device are provided by patterning an interlayer dielectric of the semiconductor device to form a contact hole that exposes a silicon-based region of a first impurity type. The exposed silicon-based region is doped with a gas containing an element of the first impurity type and a contact plug is formed in the contact hole. Contact structure for a semiconductor device are also provided that include an interlayer dielectric of the semiconductor device having a contact hole formed therein that exposes a silicon-based region of a first impurity type. A delta-doped region of the first impurity type is provided in the exposed silicon-based region. A contact plug is provided in the contact hole and on the delta-doped region.

Methods of fabricating contacts for semiconductor devices utilizing a pre-flow process

A method of manufacturing a semiconductor device having a metal layer is provided in which variation of surface morphology resulting from thermal oxidation is suppressed. The metal layer is pretreated at a first temperature so that an upper surface of the metal layer is changed into a mixed phase of metal and oxygen and becomes substantially resistant to further oxidation during a subsequent heating at a higher temperature in an oxygen atmosphere.

Method for manufacturing semiconductor devices and integrated circuit capacitors whereby degradation of surface morphology of a metal layer from thermal oxidation is suppressed

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Seoul, South Korea

Eun-ae Chung