Electronics and Telecommunications Research Institute

Eun-A Choi

Nae-Soo Kim

Deock-Gil Oh

Ji-Won Jung

Dae-Ig Chang

In-Ki Lee

Sung-Jun Cho

Tae-Gil Lee

Sang-Jin Park

Provided is a low-density parity-check (LDPC) decoding apparatus and method using a type-classified index. The apparatus includes: a memory allocating unit for multiplying reception data by an estimated channel value and storing a multiplied value in a memory including a plurality of memory block; an index storing unit for storing a Read Only Memory (ROM) index, an address index and a permutation index for the stored data; a check node updating unit for bring the stored data in parallel based on the ROM index, the address index, and the permutation index and updating a check node; and a bit node updating unit for updating a bit node based on the data stored in the memory and check node information updated in the check node updating unit.

LDPC decoding apparatus and method using type-classified index

A turbo TCM decoder for performing a soft decision without performing a sector phase quantization is disclosed. The turbo TCM decoder includes: a symbol transformer for converting a received signal to signal bits of QPSK mode by using an I-axis coordinate and a Q-axis coordinate on a constellation of the received signal; a phase sector quantizer for performing a phase sector quantization or the received signal by using the I-axis coordinate and the Q-axis coordinate; a first decoder for determining coded data by decoding the converted signal bits; a delay for delaying the quantized signal; and a second decoder for determining un-coded data by using the delayed quantized signal and the determined coded data.

Apparatus and method for decoding turbo TCM using coset mapping

Provided are an LDPC decoding apparatus and method using a sequential decoding algorithm having a partial group, capable of reducing the number of an iterative decoding by more than half without degrading the performance and increasing an amount of computation. The LDPC decoding method includes the steps of: receiving a prior probability information (channel values) based on information on channel values associated with distance between symbol signals in constellation related to the received noise and LDPC encoded data, and initializing bit nodes; dividing check nodes into partial groups before updating check node information based on the prior probability information, and performing a decoding by applying a sequential decoding algorithm; determining whether a parity check equations are satisfied; and outputting decoded messages obtained when satisfying the parity check equation or after terminating an iterative processor by a termination algorithm.

LDPC decoding apparatus and method with low computational complexity algorithm

The present invention relates to a pre-processing apparatus using nonuniform quantization of a channel reliability value and a low density parity check (LDPC) decoding system. The pre-processing apparatus can present degradation in performance and be embodied simply by performing decoding pre-process by estimating a discrete channel reliability value (L*) through nonuniform quantization of a channel reliability value based on a relations between a bit error rate (BER) estimated through a simulation performed in advance and a standard deviation (&#x3c3;) of channel noise within a predetermined range of noise estimation error and p, and bit-shifting a receiving signal as much as a discrete channel reliability value. The pre-processing apparatus includes: a channel reliability measuring unit, a nonuniform quantizing unit, a sign bit adding unit, a bit shifting unit.

Pre-processing apparatus using nonuniform quantization of channel reliability value and LDPC decoding system using the same

A structure and a method for depuncturing an input bit stream being input to a Viterbi decoder when the Viterbi decoder is designed by using a Radix-4 branch metric calculator in a method for designing the Viterbi decoder that decodes a punctured code at a high-speed, are disclosed. A depuncture structure for Radix-4 branch metric calculation in a high-speed Viterbi decoder includes four FIFOs, four multiplexers, and one Radix-4 branch metric calculator. Two input bit streams of I and Q are connected to two upper FIFOs and two lower FIFOs. An output terminal of FIFO is connected to upper and lower multiplexers of the next stage. One output terminal of each multiplexer is connected to Radix-4 branch metric calculator. As a result, Radix-4 branch metric calculation can be achieved by using the same clock as a clock speed of the input I and Q bit streams. This structure and this method can be applied to a depuncturing process for Radix-4 branch metric calculation of all punctured codes derived from &frac12; code.

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Daejon, South Korea

Eun-A Choi