National Semiconductor Corporation

Euisik Yoon

Ronald P Kovacs

Robert W Allison, Jr

Albert M Bergemont

Michael E Thomas

A dielectric structure on a substrate includes a primary dielectric layer on the substrate, the primary dielectric being a metal oxide, such as tantalum pentoxide, having a high dielectric constant, and a secondary dielectric layer, such as an oxide or nitride of silicon, on the primary dielectric layer. In one embodiment, a multi-layer structure includes a second primary dielectric layer disposed on the secondary dielectric layer, and a second secondary dielectric layer disposed on the second primary dielectric layer, each primary dielectric layer being in a first crystalline state characterized by low leakage current for a given applied electrical field. A method of forming a dielectric structure on a substrate includes forming a layer of a primary dielectric, which is a metal oxide having a high dielectric constant, forming a secondary dielectric layer on the primary dielectric layer, and annealing the primary dielectric layer.

Method of providing a dielectric structure for semiconductor devices

A method of and apparatus for processing semiconductor wafers which include observing optical characteristics of exposed undeveloped photoresist, without removing the wafers from the stepper is disclosed. The present invention includes the steps of loading a wafer having a layer of photoresist into a photolithography system, exposing the photoresist in accordance with an initial set of control parameters including exposure time, position of the wafer within the photolithography system, and/or focus change. Prior to developing the photoresist, optical characteristics of the exposed photoresist are observed using a phase contrast microscope which detects latent images. Then, according to the observations of the latent image, the initial set of control parameters are adjusted to generate a second set of control parameters.

Photolithography control system and method using latent image

A process flow for fabricating a self-aligned stacked gate EPROM cell that uses a CVD tantalum oxide film to replace ONO as a control gate dielectric. Tungsten replaces polysilicon as the control gate. Both the dielectric deposition and cell definition steps of the process flow are performed in a back-end module to improve dielectric integrity in the memory cells by minimizing high temperature exposure of the tantalum oxide film.

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Sunnyvale, CA, United States of America

Euisik Yoon