Samsung Electronics Co., Ltd.

Euibok Lee

Wandon Kim

Hoonseok Seo

Taeyong Bae

Jongmin Baek

Dohyoung Kim

Rakhwan Kim

Hyunbae Lee

YoungWoo Cho

Tsukasa Matsuda

Sunyoung Noh

Hanmin Jang

Jongseo Hong

A semiconductor device includes a substrate with an active region, a first interlayer insulating layer on the substrate, a first wiring in the first interlayer insulating layer that is electrically connected to the active region, an insulating pattern on the first interlayer insulating layer and that has a first opening exposing the first wiring, a double etch stop layer having lower and upper etch stop patterns on the insulating pattern and the first wiring, and including a second opening exposing a portion of the first wiring, a second interlayer insulating layer on the upper etch stop pattern and having a via hole connected to the second opening, the via hole having a rounded top corner region, a second wiring in the second interlayer insulating layer, and a via connecting the portion of the first wiring and the second wiring through the second opening and the via hole.

Semiconductor device with double etch stop layer and method of manufacturing the same

A semiconductor device includes a lower structure including a substrate, a first interconnection layer extending in a first direction on the lower structure, and including a first metal, a first via contacting a portion of an upper surface of the first interconnection layer and including a second metal, a second via contacting at least a portion of an upper surface of the first via and having a maximum width narrower than a maximum width of the first via, and a second interconnection layer connected to the second via and extending in a second direction. The first interconnection layer has inclined side surfaces in which a width of the first interconnection layer becomes narrower towards an upper region of the first interconnection layer, and the first via has inclined side surfaces in which a width of the first via becomes narrower towards an upper region of the first via.

Semiconductor devices

An integrated circuit (IC) device includes a first conductive line in a closed curve defining a local area on a substrate. The first conductive line has a first end portion and a second end portion. A second conductive line is outside the local area. The second conductive line has a linear line portion along the closed curve and a bulging end portion along the closed curve. The bulging end portion protrudes from the linear line portion toward the first end portion of the first conductive line in the second lateral direction and protrudes further than the first end portion to the outside of the local area. A method of manufacturing an IC device includes forming a first reference pattern having a mandrel hole. A reference spacer is formed inside the mandrel hole. A second reference pattern is formed. The second reference pattern has a shift hole.

Integrated circuit device having parallel conductive lines with bulging end portion(s) and method of manufacturing the same

A method of manufacturing a semi-damascene structure of a semiconductor device includes: forming a 1intermetal dielectric layer; forming a 1hardmask layer and at least one 1photoresist pattern on the 1intermetal dielectric layer; patterning at least one via hole penetrating through the 1hardmask layer and the 1intermetal dielectric using the 1photoresist pattern; removing the 1photoresist pattern among the 1photoresist pattern and the 1hardmask layer; forming a metal structure in the via hole such that the metal structure fills in the vial hole and extends on the 1hardmask layer; patterning the metal structure to form at least one 1trench penetrating at least the metal structure at a portion where the metal structure extends on the 1hardmask layer; and filling the 1trench with a 2inter-metal layer.

Semi-damascene structure with dielectric hardmask layer

A semiconductor device structure includes: at least one inter-metal layer stacked in a vertical direction; and avia structure penetrating the at least one inter-metal layer, wherein, in the at least one inter-metal layer, avertical side of thevia structure does not contact a barrier metal pattern while avertical side of thevia structure opposite to thevertical side of thevia structure contacts the barrier metal pattern.

Self-aligned supervia and metal direct etching process to manufacture self-aligned supervia

A method of manufacturing a semiconductor device may include: forming an interlayer insulating layer having openings on a substrate; forming a metal layer in the openings and on the interlayer insulating layer, the metal layer including a sidewall portion on a sidewall of each of the openings and a bottom portion on a bottom surface of each of the openings, wherein the bottom portion is thicker than the sidewall portion; reflowing the metal layer to form metal patterns in the openings, the metal patterns having top surfaces at a level lower than a topmost surface of the interlayer insulating layer; and/or forming capping patterns covering the metal patterns in the openings.

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Seoul, South Korea

Euibok Lee