Yonsei University

Skhynix Inc.

Eui Young Chung

Sang Woo Han

Hyeok Jun Seo

Young Min Park

Sang Hyup Lee

Soo Hong Ahn

Do Hyeon Kim

Min Jung Cho

Seong Jae Eom

Disclosed are a method for designing a cache memory structure of an artificial intelligence accelerator and an apparatus therefor. A method for designing a structure of a cache memory of an accelerator in a cache memory structure designing apparatus is a cache memory structure designing method including a memory access information extracting step of extracting a memory address of a cache memory accessed by a processing element array (PE array) at every time stamp for an application input to the accelerator, a memory access pattern determining step of determining a memory access pattern for the application based on the memory addresses of the cache memory accessed over time, and a cache structure design step of deriving a cache memory structure using a cache structure design model trained in advance based on a memory access pattern and generating cache structure design information for the cache memory structure.

Method and apparatus for designing cache memory structure based on artificial intelligence

A controller that controls a nonvolatile memory apparatus may include a first memory configured to temporarily store user data, a second memory including a plurality of memory regions composed of one or more meta regions for storing meta data and at least one spare region, and a processor configured to control the first memory and the second memory and perform first start-gap wear leveling on at least one meta region using the at least one spare region as a gap.

Controller and operating method thereof

Disclosed is a device for maintaining consistency between a host system cache and a main memory in a general-purpose computing system equipped with a hardware accelerator for processing main memory data. The device for maintaining data consistency between a hardware accelerator and a host system, which is at least temporarily implemented by a computer, includes a determination unit responsible for determining whether an address which the hardware accelerator should access is present in a cache, and a processing unit responsible for selectively performing write-back on data corresponding to the address when the address is present in the cache based on the determined result.

Device for maintaining data consistency between hardware accelerator and host system and method thereof

Disclosed is a main memory capable of speeding up a hardware accelerator and saving memory space. The main memory according to the present disclosure is at least temporarily implemented by a computer and includes a memory, and an accelerator responsible for performing an operation for hardware acceleration while sharing the storage space of a host processor and the memory.

Growing community of inventors

Seoul, South Korea

Eui Young Chung