Yonsei University

Skhynix Inc.

Samsung Electronics Co., Ltd.

Eui-Young Chung

Jeongbin Kim

Hongil Yoon

Taehee You

KiTae Kim

Youngmin Park

Seungjin Lee

Sangwoo Han

Jaewoo Park

Kangwook Jo

Kwanhu Bang

Kyungseon Cho

Younghwan Hong

Daehyung Cho

Hyeok-Jun Seo

Seok-Min Ko

Minyoung Im

Byungryul Kim

Myeongjin Kim

Sang Hyup Lee

Seong-Lyun Kim

Sang-Woo Han

JuHyung Hong

Sang-Hoon Park

Tae Yang Jeong

Gi Lee

Dae Hyung Cho

Kwangsu Kim

Byoung Jin Kim

Disclosed are a memory system for a data swap and an operating method thereof. A memory system may include a plurality of layers coupled through at least one through silicon via (TSV) channel and a swap controller configured to generate a swap control command in response to a request received from an external host and to device swap data into a plurality of data units having a predetermined size to perform a swap operation between a first layer and a second layer among the plurality of layers, wherein the first layer and the second layer include at least one swap buffer and control a movement of the plurality of data units in response to the swap control command.

Memory system for data swap and operating method thereof

A device for providing a location-based automatic participation chat room, the device, when a request to open a chat room is received along with service location information from at least one host terminal, creates at least one chat room, and sets a chat room identifier and a recognition code corresponding to each of the at least one chat room, and when at least one guest terminal accesses a location corresponding to the service location information using a pre-set participation means or the recognition code included in the participation means is received, makes the guest terminal participate in the chat room corresponding to the recognition code.

Device and method for providing automatic participation chat room

An operating method of a computing system includes storing, in a submission queue, a command entry corresponding to a request for one of input and output; fetching the command entry from the submission queue, moving data corresponding to the request within a host memory that is under control of a storage device; after moving the data, updating a completion status of the request in a completion queue; and after updating the completion queue, transferring the data between the host memory and the storage device.

Computing system with a nonvolatile storage and operating method thereof

A method for designing an FPGA may include determining blocks required for each of a plurality of applications; determining a size of the FPGA accommodating the determined blocks for each of the plurality of applications; and laying out the determined blocks for each of the plurality of applications in a block array of the FPGA.

Method for designing an FPGA

A technology mapping method for a FPGA includes converting a gate level netlist into an AND-Inverter Graph (AIG) netlist, selecting a node among nodes included in the AIG netlist, generating a cut set including one or more cuts corresponding to the selected node, selecting a best cut by sorting the cuts included in the cut set according to predetermined criteria and outputting a LUT netlist including the best cut, wherein the predetermined criteria include a maximum difference of levels of sub-cuts connected in each cut as a first criterion.

Technology mapping method of an FPGA

A semiconductor device may comprise a plurality of chips coupled in a ring structure, and the plurality of chips includes a first chip. Each of the plurality of chips may include a key port receiving or outputting a key to circulate the key through the ring structure. The first chip is configured to be in a standby state until an amount of available token becomes equal to or greater than an amount of required token to perform a specific operation in the first chip, when the first chip has the key.

Semiconductor device managing power budget and operating method thereof

A Look Up Table (LUT) includes a data storage circuit including a plurality of nonvolatile memory elements respectively corresponding to a plurality of applications, the data storage circuit being configured to select one of the plurality of nonvolatile memory elements according to an application selection signal; an amplification circuit configured to amplify a signal output from the selected nonvolatile memory element according to an enable signal output from a decoder; and a write control circuit configured to program the selected nonvolatile memory element with information corresponding to a data signal according to a write signal.

Look up table including a nonvolatile memory element, FPGA including the look up table, and method for designing the FPGA

A look up table (LUT) includes a decoder configured to decode input signals and to output decoded signals, a storage unit including a plurality of magnetic elements an being configured to select one or more of the plurality of magnetic elements in response to the decoded signals and a signal input/output (TO) unit configured to output an output signal corresponding to the selected one or more magnetic elements and to program the selected one or more magnetic elements by receiving a write signal.

Look up table including magnetic element, FPGA including the look up table, and technology mapping method of the FPGA

A semiconductor device may comprise a plurality of chips coupled in a bidirectional ring structure. The plurality of chips includes a first chip, and the first chip determines whether a token is required to perform a specific operation in the first chip. The first chip further determines whether an amount of an available token in the first chip is equal to or greater than an amount of the required token to perform the specific operation. When the amount of the available token is equal to or greater than the amount of the required token, the first chip performs the specific operation and then the first chip outputs one or both of a first portion of the available token in a first direction and a second portion of the available token in a second direction. The first direction is opposite to the second direction in the bidirectional ring structure.

The inventive concept relates to a user system including a solid state disk. The user system may include a main memory for storing data processed by a central processing unit; and a solid state disk for storing the selected data among data stored in the main memory. The main memory and the solid state disk form a single memory hierarchy. Thus, the user system of the inventive concept can rapidly process data.

Solid-state disk, and user system comprising same

A semiconductor device includes a plurality of chips including first and second chips, each of the first and second chips including a first input terminal receiving a first token input signal, a first output terminal outputting a first token output signal, a second input terminal receiving a second token input signal, and a second output terminal outputting a second token output signal. The first and second chips are coupled to each other in a bi-directional ring structure such that the first output terminal of the first chip is coupled to the first input terminal of the second chip and the second output terminal of the second chip is coupled to the second input terminal of the first chip. Each of the first and second chips performs a corresponding peak zone operation according to the first token input signal and the second token input signal.

Semiconductor device managing power budget using bi-directional ring structure and operating method thereof

A controller controls data input/output for a semiconductor memory device. The controller includes a first buffer configured to perform data transmission between an interface and the semiconductor memory device, a first control unit configured to control the semiconductor memory device according to an external request, and a second control unit configured to control the first buffer and the first control unit to simultaneously process a plurality of external requests according to a pipeline scheme.

Pipelined data I/O controller and system for semiconductor memory

A data storage device includes a first memory device configured to store data having a first property, and a second memory device including a first block configured to store data having a second property and a second block configured to store data transferred from the first memory device.

Data storage device and operating method thereof

A data storage device includes a first memory device configured to store data having a first property, a second memory device configured to store data having a second property, and a controller. The controller selects data stored in the first memory device, and transfers the selected data to the second memory device or stores the selected data in another physical location of the first memory device selectively depending on an update count (UC) of an address at which the selected data is stored.

Growing community of inventors

Seongnam, South Korea

Eui-Young Chung