Hynix Semiconductor Inc.

Eui Suk Kim

Won Kyung Kang

A data output circuit in an NAND flash memory device is disclosed. The data path circuit in a flash memory includes at least one switching means configured to output one or more internal address signals in accordance with a data output control signal, and one or more data output circuit configured to output data when a specific internal address signal is outputted through the switching means.

Data path circuit in a flash memory device

Disclosed are a method of controlling a page buffer having a dual register and a control circuit thereof. In the present invention, during a normal program operation, a normal program operation is performed through the same transmission path as a data transmission path along which data is outputted from bit lines of a memory cell array to a YA pad according to a signal PBDO used in a read operation. A program operating time can be reduced and the whole program operation of a chip can be thus reduced. It is also possible to reduce current consumption by shortening a data path during the normal program operation.

Method of controlling page buffer having dual register and circuit thereof

A redundancy circuit for a NAND flash memory device reduces a test time and production time of the device, by performing a redundancy operation through a repair select unit using a cam cell. In addition, the redundancy circuit employs a repair method using a redundancy cam which can perform the repair operation much faster than a general repair method using fuse cutting.

Redundancy circuit for NAND flash memory device

A page buffer in which the value of data that have been latched in a register of a page buffer is not changed by slowly transmitting data to the register in a check board program operation of a NAND flash memory device. The page buffer includes a first register having a first input unit for alternately receiving program data and erase data, and a second register having a second input unit for alternately receiving program data and erase data. Charge devices are respectively coupled to the first and second input units so that the program data or erase data are slowly input to the first or second input unit.

Page buffer for preventing program fail in check board program of non-volatile memory device

A boosting circuit is provided that includes a reference voltage generating circuit unit to generate a reference voltage, a voltage boosting circuit to output a given boosting voltage, and a sensing circuit to sense a flash memory cell according to the reference voltage and the boosting voltage of the voltage boosting circuit. An output signal of the sensing circuit is changed depending on the boosting voltage of the voltage boosting circuit applied to a gate terminal of the flash memory cell. The boosting circuit also includes a switching circuit to apply the boosting voltage of the voltage boosting circuit or a power supply voltage depending on the boosting voltage of the voltage boosting circuit and the output signal of the sensing circuit.

Boosting circuit

The present invention discloses a method and device for preserving a word line pass bias using a ROM block in a NAND-type flash memory. The method for preserving the word line pass bias includes a step for closing a precharge transistor of a precharge circuit before the operation of a pass transistor for precharging a selected word line, by separately outputting from the ROM block a program precharge control signal transmitted to a group access signal generation circuit for outputting a group access signal and a program precharge control signal transmitted to a block word line, and synchronizing the signals in a synchronization circuit. Accordingly, time mismatching in the program and read operations of the NAND-type flash memory is prevented, and a predetermined voltage precharged to the selected block word line is precisely inputted to a specific cell and preserved.

Method and device for preserving word line pass bias using ROM in NAND-type flash memory

A boosting circuit is disclosed. The boosting circuit comprises a reference voltage generating circuit unit for generating a reference voltage according to an address transition detection signal that is delayed by a given time, a first boosting means for outputting a given boosting voltage according to the address transition detection signal and an inverted signal thereof, a sensing circuit for sensing a flash memory cell according to the reference voltage and the boosting voltage of the first boosting means, wherein the output signal of the sensing circuit is changed depending on the boosting voltage of the first boosting means applied to a gate terminal of the flash memory cell, a switching circuit for applying the boosting voltage of the first boosting circuit or the power supply voltage depending on the boosting voltage of the first boosting circuit and the output signal of the sensing circuit, and a second boosting means for supplying the power supply voltage to an output terminal according to the address transition detection signal, wherein the second boosting means is boosted according to the boosting voltage of the first boosting circuit or the power supply voltage to output the boosting voltages of two levels to the output terminal. Therefore, it is possible to prevent stress from being applied to the word lines of the cell due to a high voltage applied to the word lines, prevent unnecessary consumption of current and secure the read-out margin.

Growing community of inventors

Kyungki-do, South Korea

Eui Suk Kim