Korea Advanced Institute of Science and Technology

Eui Sik Yoon

Jun Bo Yoon

Chul Hi Han

Choong Ki Kim

Kwang-Seok Yun

Disclosed is a micro-fluidic chip for high-throughput screening and high-throughput assay, in which its structure is improved, thereby enhancing the efficiency of high-throughput screening and high-throughput assay. The micro-fluidic chip includes a well for isolating a specimen. The well can be arranged in a one- or two-dimension. A specimen-isolating means is disposed above the well and is movable upwards and downwards. An opening and closing means for moving the specimen-isolating means upwards and downwards is disposed above the specimen-isolating means. An inlet for injection the specimen and an outlet for discharging an excess of the injected specimen are provided. A reagent-injecting passage for injecting a reagent and a reagent-discharging passage for discharging the reagent are also provided.

Microfluidic chip for high-throughput screening and high-throughput assay

A method for manufacturing a semiconductor device where a passive element, such as, an inductor, is floating over a substrate, where an integrated circuit is formed, such that the overall area of the semiconductor device may be highly reduced. According to the present invention, a first metal layer is formed on the substrate, a first masking layer is formed on a portion of the first metal layer, a second metal layer is formed on other portion of the first metal layer on which the first masking layer is not formed, and a second masking layer is formed on the first masking layer and the second metal layer. Then, the first masking layer and a portion of the second masking layer which includes a portion which covers the first masking layer is removed, a third metal layer is formed on portions of the first and second metal layers which are exposed by the step of removing the first masking layer and the portion of the second masking layer. Finally, the second masking layer, the second metal layer; and the first metal layer except a portion which the third metal layer covers are removed. In this way, the area for integrating various passive elements can be saved and the overall area for the semiconductor device including the integrated circuit and the passive elements may be reduced.

Growing community of inventors

Daejeon, South Korea

Eui Sik Yoon