Samsung Electronics Co., Ltd.

Eui-Seung Kim

Chan-Yong Kim

Ji-Sung Kim

Jung-Hyun Kim

Jong-cheol Kim

SeEun O

Sang-Joo Jun

A sense amplifier circuit of a nonvolatile semiconductor memory device is provided. The sense amplifier circuit includes a reference voltage generator, a sensing voltage generator and a comparator. The sensing voltage generator outputs a sensing voltage to a sensing node depending on a current flowing through a data line. A load transistor supplying a current to the data line is directly connected to a clamping node. The load transistor is included in a current mirror circuit. In a read operation, a low voltage drive operation is performed and a sensing speed and power consumption are properly controlled.

Sense amplifier for nonvolatile semiconductor memory device

An integrated includes a memory cell, a bit line connected to the memory cell, a boosting circuit to boost the bit line up to a boosting voltage during a pre-charge operation pre-charging the bit line, and a regulation circuit connected between the bit line and an output terminal and determines a logic level of the output terminal according to the voltage of the bit line.

Integrated circuit and apparatuses including the same

A semiconductor device includes a test pattern decoding unit and a scan chain unit. The test pattern receives a scan-in pattern from an external test device and generates a test pattern based on the scan-in pattern and a scan-out pattern. The scan-in pattern is decoded based on a seed pattern and an expectation pattern. The scan chain unit performs logical operation based on the test pattern and feedbacks the scan-out pattern to the test pattern decoding unit.

Semiconductor device and test system for testing the same

A smart card system having: a smart card including a security logic circuit to detect an external attack; and a reader communicating with the smart card. The security logic circuit detects the external attack by measuring the external input capacitance through an input/output pad of the smart card and comparing the external input capacitance to the input capacitance of the reader. This improves the security of the smart card system.

Smart card system and operating method thereof

A relaxation oscillator compensates for system delay. The relaxation oscillator includes first and second input signal units that generates first and second capacitor voltages, a delay compensation unit that receives a reference voltage and the first and second capacitor voltages and that generates a compensation voltage. In certain embodiments, a voltage generating unit applies the reference voltage to the delay compensation unit, and a latch unit stores first and second comparison signals compared by the first and second input signal units and transmits a clock signal and a inverted clock signal to the first and second input signal units. The first and second input signal units compare the first and second capacitor voltages with a compensation voltage transmitted from the delay compensation unit.

Relaxation oscillator for compensating system delay

Voltage glitch detection circuits and methods thereof. The voltage glitch detection circuit may include a monitoring memory array including at least one memory cell storing reference data, a monitoring sense amplifier receiving stored reference data from the monitoring memory array, amplifying the received stored reference data in response to an operation control signal and outputting data based on the reference data, a data storage circuit including at least one latch to store the reference data and a comparator circuit receiving and comparing the data output from the monitoring sense amplifier and the stored reference data from the data storage circuit, and outputting a detection signal based on the comparison. The voltage glitch detection circuit may include a first storage unit configured to latch a first voltage, a second storage unit configured to latch a second voltage, a first comparator circuit first comparing the latched first voltage with a first reference voltage and outputting a first comparison result, a second compariator circuit second comparing the second voltage with a second reference voltage and outputting a second comparison result and a third comparator circuit third comparing the first and second comparison results and outputting a reset detection signal based on the third comparison.

Voltage glitch detection circuits and methods thereof

A demodulator for processing a PWM (pulse width modulation) signal includes a variable capacitor, a charging unit, a discharging unit, and a tuner. The charging and discharging units charge or discharge the variable capacitor depending on the PWM signal. The tuner determines a capacitance of the variable capacitor and a discharge current of the discharging unit for proper operation of the demodulator in various RF environments.

Apparatus and method for adaptive demodulation of PWM signal

An internal voltage converter and method is provided capable of reducing power consumption using a selective voltage reference, a semiconductor device including the internal voltage converter. A semiconductor device uses the internal voltage converter which discriminates an IVC stand-by state from a normal operation state, selects a voltage reference with low power consumption among selective voltage references in the IVC stand-by state, and generates an internal voltage.

Semiconductor device having an internal voltage converter, and method therefor

A voltage-glitch detection circuit includes a voltage comparator having two input terminals with different capacitance resistance charge/discharge time. Voltage dividers are coupled to the two input terminals of the voltage comparator respectively, and commonly receive a supply voltage. One of the voltage dividers is supplied to the voltage comparator as a reference voltage of the voltage comparator, and the other is supplied as a glitch detection voltage to the voltage comparator.

Growing community of inventors

Suwon-si, South Korea

Eui-Seung Kim