Skhynix Inc.

Eui Cheol Lim

Myoung Seo Kim

Sun Woong Kim

Chang Hyun Kim

Seung Yong Lee

Hyung Sik Won

Ji Hoon Nam

Young Jung Choi

Jae Hoon Kim

Choung Ki Song

Joon Seop Sim

Sung Woo Hyun

Mi Seon Han

Hyeong Tak Ji

A data processing system including a shared memory; a host processor configured to possess an ownership of the shared memory, and process a first task by accessing the shared memory; a processor configured to possess the ownership transferred from the host processor, and process a second task by accessing the shared memory; and a memory controller coupled among the host processor, the processor, and the shared memory, and configured to allow the host processor or the processor to access the shared memory according to the ownership.

Memory system adjusting check period for remaining throughput and data processing system including the memory system

A system for classifying data may include a memory, and a processor configured to determine a scan target including a data group selected from among data groups stored in the memory, based on a result of a comparison between first similarities of data groups stored in the memory and an externally received query, and a minimum value of second similarities of pieces of data included in a data group having a maximum value of the first similarities and the query, and to output, as result data responding to the query, scan data selected depending on a reference number of pieces of scan data from among pieces of scan data in the data group included in the scan target.

System for classifying data based on a classification algorithm and method of operating the same

An arithmetic device includes a multiplying-accumulating (MAC) operator and an activation function (AF) circuit. The MAC operator performs a MAC arithmetic operation for weight data and vector data to generate an arithmetic result signal. The AF circuit stores a look-up table for an activation function, adjusts a number of logic level combinations of an input distribution signal that correspond to each logic level combination of the output distribution signal, among a plurality of logic level combinations of the output distribution signal, based on an input range of the activation function. The AF circuit selects and outputs the output distribution signal that corresponds to the input distribution signal based on the look-up table. The input range of the activation function is based on a relative number of errors that occur.

Arithmetic devices for neural network

A memory module may include J memory chips configured to input/output data in response to each of a plurality of translated address signals; and an address remapping circuit configured to generate a plurality of preliminary translated address signals by adding first correction values to a target address signal provided from an exterior of the memory module, and to generate the plurality of translated address signals by shifting all bits of each of the plurality of preliminary translated address signals so that K bits included in a bit string of each of the plurality of preliminary translated address signals are moved to other positions of each bit string.

Semiconductor memory apparatus, memory module, and memory system including memory module

A storage device can be designed to reduce latency in a read operation. Such a storage device can include: a memory device including a plurality of pages that include a first page and a second page different from the first page, each page including a plurality of memory cells that are configured to store data; and a memory controller in communication with the memory device and for sequentially storing result values of a function with respect to a plurality of input values in the plurality of memory cells, and controlling the memory device to store a result value in a last area of the first page and a start area of the second page.

Storage device and operating method thereof

A memory system is disclosed, which relates to technology for implementing data communication between memory devices. The memory system includes a plurality of memory devices and a memory controller. The memory devices allow a data packet composed of data and header information to be directly communicated between the memory devices. The memory controller transmits the data packet to a source memory device from among the plurality of memory devices, and receives the data packet from a last memory device from among the plurality of memory devices. Each of the memory devices hashes the header information such that the data is accessed, using a result of the hash, in address regions located at different positions.

Memory system

Data processing system accessing shared memory by using mailbox

A memory system includes a non-volatile memory device and a controller. The non-volatile memory device includes a plurality of memory regions, each memory region including a plurality of cells commonly coupled to a word line. The controller generates a plurality of candidate data sets based on source data, determines a number of vulnerable cells corresponding to each of the plurality of candidate data sets, and stores a candidate data set having a smallest number of vulnerable cells into a target memory region among the plurality of memory regions.

Memory system and operating method thereof

A memory system is disclosed, which relates to technology for an accelerator of a high-capacity memory device. The memory system includes a plurality of memories configured to store data therein, and a pooled memory controller (PMC) configured to perform map computation by reading the data stored in the plurality of memories and storing resultant data produced by the map computation in the plurality of memories.

Growing community of inventors

Icheon, South Korea

Eui Cheol Lim