Altera Corporation

Eugene Y Chen

Dominik J Schmidt

Richard C Saito

Perry Chun

An method of creating a physical layout of an integrated circuit. A schematic file () is mapped directly to a physical layout using the location of elements and routing of interconnections as specified in the schematic file (). The method takes advantage of constraints on the schematic design to provide the layout file () quickly, without complex routing programs. Design rules violations are anticipated and corrected in some cases. In other cases, the design rule violations are annotated, if the designer intentionally placed them in the design.

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San Jose, CA, United States of America

Eugene Y Chen