Cisco Technology, Inc.

Amdahl Corporation

Amdahl Corportion

Eugene T Wang

Gene K Chui

Lambert Fong

Stephen S Si

Norman Tang

David Lai

Nang Tran

Vu Nguyen

David Anthony Hughes

Madhav V Marathe

Gary A Woffinden

Alex Van Truong

Durai Chinnaiah

Quang H Nguyen

Jayakumar Jayakumar

Gurmohan Singh Samrao

Frank Chui

Gary Kipnis

John Sandoval

Matt Noel

Jongwen Chiou

Tien D Tran

Lionel A King

Dan Klausmeier

Hiep Le

Daryn Lau

Greg Aldrich

Gregory Aldrich

Hariprasad Ginipalli

A backplane having a switch card interface and an adapter card interface where the switch card interface has input/outputs in an arrangement that functionally mate to a networking layer system switch card and a physical layer system switch card. The adapter card interface is coupled to the switch card interface. The adapter card interface has input/outputs in an arrangement that functionally mates to a networking layer system adapter card and a physical layer system adapter card. A method that involves forming a first and second backplane according to a manufacturing process, integrating the first backplane into a networking layer system switch, and integrating the second backplane into a physical layer system switch.

Common backplane for physical layer system and networking layer system

One embodiment of the invention includes a system for overriding an operation of an electronic device. The system includes an override hardware logic that is communicatively coupled with a monitoring system. The monitoring system can output an electronic command signal in response to a detected point of failure associated with the system. In response to receiving the electronic command signal, the override hardware logic can override the operation performed by the electronic device in order to compensate for the detected point of failure.

Method to increase system availability of critical hardware components

A system and method for using a single shared buffer to service multiple destinations for a telecommunications switch is disclosed. Upon receiving a cell of data to be sent to a destination, an interface stores the cell in a shared buffer. The address of the cell in the buffer is stored in a queue array. The address of the buffer address in the queue array is stored in a head array and a tail array. A threshold register tracks the global threshold for the total number of cells in the shared buffer and a destination threshold for each destination. The buffer can broadcast a data cell to a single location or send the same cell to multiple locations.

Shared buffer switch interface

Virtual local area network (VLAN) identifications (VIDs) used in a local area network (LAN) are identified. The LAN is connected to a connection-oriented wide area network (WAN). Each VLAN supports multiple priorities. For each VID, each of the priorities is mapped to a service type available in the WAN. Virtual connections (VCs) are set up based using a combination of the VID and the mapping of the priorities to the service types.

End-to-end preservation of VLAN priority in connection-oriented networks

A method and apparatus for providing programmable memory functions for bi-directional cell traffic in a switch platform are provided, wherein a parameterized bi-directional FIFO unit controls cell traffic in a switch platform using a first and a second unidirectional FIFO buffer. The first and second unidirectional FIFO buffers each comprise asynchronous read and write ports. A cell size and a word size of the first and second unidirectional FIFO buffers are programmable. The bi-directional FIFO unit is coupled to write at least one cell from and read at least one cell to at least one asynchronous transfer mode (ATM) interface, at least one frame relay interface, at least one voice interface, and at least one data interface. As such, the first unidirectional FIFO buffer is coupled to write at least one cell from, and the second unidirectional FIFO buffer is coupled to read at least one cell to an ATM interface, a frame relay interface, a voice interface, and a data interface. The first unidirectional FIFO buffer is coupled to read at least one cell to at least one switch, and the second unidirectional FIFO buffer is coupled to write at least one cell from at least one switch, wherein the switch handles cells from sources having a number of bandwidths. The switch is coupled to route the at least one cell between an OC12 trunk line and at least one service module. The service module is coupled to provide the cell to at least one service subscriber using T1, E1, T3, E3, OC3, and OC 12 ports.

Method and apparatus for providing programmable memory functions for bi-directional traffic in a switch platform

An apparatus is described comprising an ingress port and a plurality of switch planes where each of the switch planes has a dedicated scheduler and each of the switch planes are communicatively coupled to the ingress port. The switch planes may further have at least one input control port and at least one output control port where each of the input control ports are coupled to each of the output control ports in a crossbar arrangement. The communicative coupling may further comprise one of the input control ports coupled to the ingress port. Furthermore, the ingress port may have at least one unicast queue which is dedicated to a specific egress port. The ingress port may also have a multicast queue. The dedicated scheduler may further comprise a pointer to determine priority between multicast and unicast traffic, a pointer to determine priority between contending input control ports having multicast traffic and/or a pointer for each of the output control ports to determine priority between contending input control ports having unicast traffic. The apparatus may also further comprise a plurality of ingress ports where each of the ingress ports are communicatively coupled to one of each of the input control ports.

Crosspoint switch with independent schedulers

An apparatus and method of compensating for differences in circuit routing path lengths is described. In one embodiment, a latch is inserted between reset signal generating logic and a pair of flip-flops. When a reset signal is generated, the reset signal is held inside the latch until both flip-flops are reset. A latch reset signal may be generated by the flip-flops to clear the latch. The circuit may be configured to ensure that both flip-flops are reset before the reset signal is disabled.

Asynchronous phase detector for a PLD independent of timing requirements

A method and apparatus for rate-based cell traffic arbitration in a switch are provided, wherein arbitration is provided between eight traffic sources in the form of eight cell bus service modules on the same cell bus. A cell bus controller (CBC) is programmed with an 8-bit Relative Service Delay (RSD) value for each of the eight service modules. The value for each RSD is calculated based on the bandwidths allotted for each service module. This RSD value determines the portion of the total bandwidth of the switch platform reserved for the respective service module. Furthermore, each service module uses an 8-bit Service Delay Accumulator (SDA) register. The SDA register of each service module is configured using an SDA value, wherein the SDA register keeps track of when each of the service modules should receive service. The SDA value is calculated at each cell bus frame time for each of the service modules based on the RSD value for each of the service modules, a request for service, and the minimum SDA value among the service modules during a cell bus frame time. If the bandwidth is under-subscribed, the remaining bandwidth is shared among all eight service modules according to the RSD value of each service module. If the bandwidth is over-subscribed, each service module will have the assigned bandwidth portion decreased according to the RSD values.

Method and apparatus for rate-based cell traffic arbitration in a switch

A method and apparatus for routing cells having different formats among service modules of a switch platform are provided. The cells are routed among service modules of a switch by a cell bus controller (CBC) using a first memory to convert an address having a first format into an address having a second format. The address having the first format is received in a header of a cell, and the address format comprises a 17-bit cell bus logical connection number of a destination port. The address having the second format is a 16-bit UDF used by a switch of the switch platform. The address having the first format is used to form a third address that is used to access the first memory. The data located at the third address of the first memory is a 16-bit UDF used to address the switch. A second memory is used to convert an address having the second format into an address having the first format. The address having the second format is used as a fourth address to access the second memory. The data located at the fourth address of the second memory is a 32-bit cell bus header that addresses a destination port. The destination port is at least one service module of the switch platform. The first and second memory comprise an external random access memory.

Method and apparatus for routing cells having different formats among service modules of a switch platform

A method and apparatus for providing cell bus management in a switch platform are provided. Each unidirectional FIFO buffer of a cell bus controller outputs a write port cell count from a write port. A cell count value is programmed at which the write port cell count is outputted. When the write port cell count indicates that the FIFO buffer can not accept additional data or cells, a master bidirectional FIFO unit ceases reading cells to a unidirectional FIFO buffer of the slave bidirectional FIFO unit in response to the write port cell count. Furthermore, the master bidirectional FIFO unit disables a corresponding switch from routing cells to the slave bidirectional FIFO unit in response to the write port cell count; the switch routes the cells to another of the slave bidirectional FIFO units. The master bidirectional FIFO unit resumes reading cells to the second unidirectional FIFO buffer of the slave bidirectional FIFO unit in response to a write port cell count indication that the FIFO buffer can accept additional data or cells. In response, the master bidirectional FIFO unit enables an associated switch to route cells to the slave bidirectional FIFO unit.

System for providing cell bus management in a switch platform including a write port cell count in each of a plurality of unidirectional FIFO for indicating which FIFO be able to accept more cell

A method and apparatus for providing asynchronous memory functions for bi-directional cell traffic in a switch platform are provided, wherein a parameterized bi-directional FIFO unit controls cell traffic in a switch platform using a first and a second unidirectional FIFO buffer. The first and second unidirectional FIFO buffers each comprises asynchronous read and write ports. A cell size and a word size of the first and second unidirectional FIFO buffers are programmable. The bi-directional FIFO unit is coupled to write at least one cell from and read at least one cell to at lest one asynchronous transfer mode (ATM) interface, at least one frame relay interface, at least one voice interface, and at least one data interface. As such, the first unidirectional FIFO buffer is coupled to write at least one cell from, and the second unidirectional FIFO buffer is coupled to read at least one cell to an ATM interface, a frame relay interface, a voice interface, and a data interface. The first unidirectional FIFO buffer is coupled to read at least one cell to at least one switch, and the second unidirectional FIFO buffer is coupled to write at least one cell from at least one switch, wherein the switch handles cells from sources having a number of bandwidths. The switch is coupled to route the at least one cell between an OC12 trunk line and at least one service module. The service module is coupled to provide the cell to at least one service subscriber using T1, E1, T3, E3, TC3, and OC 12 ports.

Method and apparatus for providing asynchronous memory functions for bi-directional traffic in a switch platform

A bypass means is provided for bypassing a system clock disabling signal around a conventional system clock disabling signal processing path to reduce the amount of delay between the occurrence of the disabling signal and a stopping of the system clock.

Apparatus and method for immediately stopping clocks

A clock distribution system for reducing clock skew between tightly coupled central processing units in a multi-processor system. The multi-processor system includes (1) a configuration processor for generating a first configuration signal and a second configuration signal, a first clock, a second clock, (2) a first processor having a first central processing unit, (3) a second processor having a second central processing unit, (4) a first clock generator for generating a first delayed clock signal from the first or second clock in accordance with the configuration signals, and (6) a second clock generator generating a second delayed clock signal from the first or second clock in accordance with said configuration signals. The clock distribution system comprises a distribution means for receiving the first delayed clock signal, the second delayed clock signal and the configuration signals, and for distributing in accordance with the configuration signals either the first delayed clock to the first central processing unit and the second delayed clock to the second central processing unit, or the first delayed clock signal to both the first and second central processing unit or the second delayed clock signal to both the first and second central processing unit.

Clock distribution system for reducing clock skew between processors in

A selectable timing delay system which provides for delaying an input signal a specified length of time within a specified tolerance wherein the range and resolution of the selectable timing delay system are so specified that the selected delay within the selected tolerance is obtainable regardless of the relative speed of the integrated circuit chips used in forming the selectable timing delay system.

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Fremont, CA, United States of America

Eugene T Wang