International Business Machines Corporation

Eugene S Schlig

George R Stilwell, Jr

James Lawrence Sanford

Savvas G Chamberlain

Ying L Yao

Frank Robert Libsch

Keith S Pennington

James M White

A pixel circuit comprises an organic light emitting diode (OLED), and a static memory for storing data that represents an operational state of the OLED. In alternative embodiments, a pixel circuit may include a complementary metal oxide semiconductor (CMOS) circuit for controlling the OLED, a protection circuit for protecting the CMOS circuit from an over-voltage condition, and a current source with a field effect transistor (FET) having a static gate to source voltage that is greater than a threshold voltage of the FET.

Low-power organic light emitting diode pixel circuit

An AMLCD display and bootstrapped pixel drive method incorporating pixel inversion. Each of a plurality of pixel assemblies arranged in a matrix of rows and columns includes a display element having a display electrode, and a semiconductor device having a control port, an input port and an output port, with each output port connected to a corresponding display electrode. Each of a plurality of bootstrap lines are additionally connected to a display electrodes of a plurality of rows of pixel assemblies, and a data line connects each input ports of pixels arranged along a column. A plurality of gate lines is provided with each gate line associated with a row of pixels in the matrix and connected to control ports of pixel assemblies in the row for receiving gate line pulses. The control ports of semiconductor devices associated with pixels located on two adjacent rows are alternately connected to either one of two associated gate lines in an interleaved fashion. A bootstrap pulse in timed relation with gate line pulses applied to each of two gate lines associated with the pixels of two adjacent rows is applied to the bootstrap lines in a timed relation such that display electrodes of alternately connected interleaved pixels of two adjacent rows shift in voltage in a first time frame and successive time frames, and enables display electrodes of remaining alternately connected interleaved pixels of two adjacent rows of pixels to shift in voltage in a second time frame and successive second time frames.

Active matrix liquid crystal display incorporating pixel inversion with

An active matrix liquid crystal display (AMLCD) and driving method is disclosed. The AMLCD has matrix-arranged pixel assemblies each having display electrodes. A gate line for carrying gate line pulses is connected to a control port of a row of semiconductor devices, which may be thin film transistors (TFTs). Each TFT has an output port connected to the display electrodes. In addition, a data line is connected to an input port of a column of the TFTs. A bootstrap line is capacitively connected to the display electrodes of adjacent rows. This reduce the number of bootstrap lines to half the number of gate and data lines. A bootstrap pulse timing and generating circuit is connected to the bootstrap line to provide a bootstrap pulse that shifts voltages on the display electrodes in only one direction. The bootstrap pulse has a first edge of a first polarity occurring before or during gate pulses carried on a gate line, and a second edge of a second polarity occurring after the gate line pulses.

Active matrix liquid crystal display with reduced drive pulse amplitudes

A threshold correcting reference voltage generator in which a capacitor is charged from a first voltage source to a voltage above the desired corrected reference voltage by means of a charging transistor controlled by a clock pulse. A metering transistor has its drain and gate electrodes connected to the capacitor either directly or through a blocking transistor. The source of the metering transistor is connected to a second voltage source which has a value below the desired corrected reference voltage. The charging transistor is then turned off and the blocking transistor, if present, turns on. Charge flows from the source to the drain of the metering transistor, reducing the capacitor voltage until the metering transistor just turns off. At this point the capacitor voltage is higher than the second voltage source by the threshold voltage of the metering transistor. This capacitor voltage is the desired corrected reference voltage; its value depends directly on the magnitude of the metering transistor threshold voltage. Finally the blocking transistor, if present, turns off to isolate the capacitor. The purposes of the blocking transistor are to avoid the direct flow of current between the first and second voltage supplies when the charging transistor is turned on, and to protect the output from errors due to subthreshold conduction in the metering transistor.

Threshold correcting reference voltage generator

A circuit for sampling monotonic input voltage changes and holding an output precisely derived from the sampled input change. The output change may be of the same polarity as the input, or inverted, and in the inverting mode of operation may exhibit highly accurate gain or attenuation. A single complementary metal-oxide-semiconductor (CMOS) embodiment may be configured to operate with positive or negative input changes and to present normal or inverted outputs, according to the application of various clock or control signals. Alternatively, subsets of that circuit provide subsets of the operating modes. The circuit operates by adding measured amounts of charge to, or removing it from a capacitor under the control of the input signal. Additional functional capabilities are capture and hold of input maximum or minimum, and accurate setting or restoration of the dc level of the output. Multiple stages may be cascaded, and the circuit may be designed for large bandwidth without introducing pedestal errors due to channel charge.

Charge metering sampling circuit and use thereof in TFT/LCD

A data line driver circuit having application in active matrix displays, such as thin-film transistor liquid crystal displays, uses charge metering techniques to achieve high precision and analog pipelining. Pipelining permits both the digital-analog conversion function and the presentation of the analog output to the display data line each to occupy most of the display's line time. The requirement of liquid crystals for periodic inversion of the net applied voltage is accommodated either by the circuits alone or with the display common electrode driven by a square wave.

Pipelined charge metering digital-to-analog data line driver

A D/A converter which develops the analog output by summing binary-weighted packets of electrical charge. Charge metering techniques are used to generate and sum the charge packets. It is particularly suited to application in the data line driver circuits of thin-film transistor liquid crystal displays. Various embodiments use single or multiple charge packet generators, and the multiple version may generate the packets for the various bits simultaneously, For the highest speed, or else sequentially, for the largest voltage dynamic range.

Charge summing digital to analog converter

An electronic imaging system develops red, green and blue images of a document in a single pass of the document through the system. The system includes an image sensor which has three time delay and integration (TDI) sensor arrays. Each sensor array is configured to have two optically masked rows of charge coupled devices (CCD's) for every row of CCD's that is used for imaging. The sensor arrays are arranged so that the first row of imaging CCD's on any two successive arrays are separated by a distance of an integer, K, times three times the height of a picture element (pel) of the image of the document that is projected onto the image sensor, plus or minus one pel height. The spectral component of the image of the document that is projected onto the image sensor is changed in sequence from red, to green, to blue. As the spectral component projected onto the image sensor is changed, the image of the document is scanned down the image sensor by a distance of one pel height. By this scheme, each line of pels in the document is imaged in each of the sensor arrays in a respectively different spectral component. A document may be imaged in all three colors in a single pass through the system without having dedicated filters for each of the separate sensor arrays.

Single-scan time delay and integration color imaging system

In the present invention, a method is set forth for the generation of an average signal for the pels of a neighborhood, i.e., a matrix array, without corrupting individual pel values. The system which performs the method includes a metering circuit, an output register, and a filtering array. The metering circuit transfers a fixed proportion of charge signals representing a pel row in parallel from the CCD array to the filtering array. The remaining charge signals remain in an output register, which outputs them as representations of the individual pels of the image. One type of filtering operates by averaging over non-overlapping regions within the image. Charge signals which have been transferred by the metering circuit are added together along the vertical axis and are transferred to a vertical average register, whereupon, this value is serially shifted out of the vertical average register and into a horizontal summer. The horizontal summer adds the output charge along the horizontal axis. This results in an average of the individual pel values within a region of the image which is outputted form the device. Another type of filtering operates by averaging overlapping windows within the image. The charge signals from the metering circuit are split into multiple portions, each of which contributes to a different vertical sum for an averaging window. The vertical sum charge signals are split into multiple portions, each of which contributes to the area sum for an averaging window, which is created by horizontal summing performed in parallel. The resulting area averages are outputted.

Averaging array for CCD imagers

Two unknown charge packets are stored in adjacent potential wells of equal depth in a charge coupled device. The charge packets are then merged by changing the potential on an intermediate merge electrode to remove a potential barrier between the two wells. The potential barrier is then re-established, and a current is induced through one of the electrodes which established the two wells of equal depth, and that current is integrated as a measure of the original absolute difference between the two charge packets.

Absolute charge difference detection method and structure for a charge

This CCD structure comprises a substrate floating diffusion region from which an output signal is taken and a drain diffusion spaced apart from the output diffusion and from which the charge is returned. An electrode to be pulsed is placed immediately preceding the floating diffusion and a plurality of electrodes is interposed between the two diffusions. The first such electrode beyond the output floating diffusion is operated as a reset pulse gate electrode and the last such electrode before the drain diffusion is operated as a drain pulse gate electrode, while the intermediate electrode(s) have phased clock pulses applied thereto in synchronism with such phased clock pulses applied to other electrodes of the overall CCD circuit arrangement. The preceding pulsed electrode serves to extend the lower limit of the potential change of the floating diffusion. The interposed electrodes permit signal charge to be transferred out of the floating diffusion into a gate-induced potential well instead of directly into the drain diffusion, extending the upper limit of potential change of the floating diffusion. Further, the drain gate isolates the drain diffusion from the preceding final CCD stages thereby obviating 'charge sloshing'.

Charge coupled device output circuit structure

A pipelined charge coupled analog to digital converter which provides a plurality of serially arranged pipelined stages that are connected to pass signal and reference charge packets from stage to stage in a serial progression. The pipelined analog to digital converter includes one stage for each bit desired in the output bit stream, and thus, an analog to digital converter providing an n bit digital word corresponding to the input analog signal charge, includes n stages. While the time necessary to perform the analog to digital conversion is the sum of operating times of all the stages, because the converter is pipelined, each successive n bit digital word representing a different successive charge packet is produced succeeding a preceding digital word representing a preceding signal charge packet, by a delay equal to the processing time of only a single stage. Thus, a charge coupled A/D system is provided including a plurality of pipelined stages for performing successive approximations on a reference charge Q.sub.r and an input analog signal charge Q.sub.s wherein said pipelined stages include charge processing means each coupled only to directly adjacent stages for performing an inequality function to provide a bit string b.sub.1 through b.sub.n representing a digital representation of said input analog signal charge Q.sub.s.

Pipelined charge coupled to analog to digital converter

A charge coupled device analog-to-digital converter includes a plurality of charge storage stages that are arranged in a serial pipeline register and are connected to pass input source charges from stage to stage down the pipeline register. A reference charge generator and a charge splitter at each stage generate two fixed reference signals. The first of the reference signals is compared by a comparator to a source charge that is temporarily stored at the stage. The comparator generates a binary 1 if the source charge is greater than or equal to the first reference charge and a binary 0 if the source charge is less than the first reference charge. If a binary 1 is generated, only the stored contents of the stage pass to the next successive stage. However, if a binary 0 is generated, the charge contents of the stage is passed to a next successive stage and the second reference charge is also passed by a transfer gate to the next successive stage, where the charges are combined. Buffer registers are provided to temporarily store the output bits of the comparators of the stages to form a digital word for each source charge packet as the packet and associated added charge components leave the pipeline.

Fast charge transfer analog-to-digital converter

A multiple access store having bipolar monolithic memory cells. Each cell includes a memory flip-flop comprised of cross-connected NPN transistors. A single concurrent read and write for each cell is achieved by a pair of accessing transistors, one accessing transistor of the pair connected at its base to the base of one of the flip-flop transistors and the other accessing transistor of the pair connected at its base to the base of the other of the flip-flop transistors. Each accessing transistor of an accessing transistor pair is connected at its collector to an associated bit/sense line. The emitter of each of the accessing transistors of an accessing transistor pair are connected together and the connected emitters are connected to a device that supplies a current supply to the emitters in response to a word signal. The emitters of the cross-connected flip-flop transistors are connected to an associated mode select line over which is applied a signal having a potential defining a write mode condition and a signal having a lower potential defining a read mode condition for the cell. Each pair of bit/sense lines and associated pair of accessing transistors that is added to each of the cells of a memory array may be operated to add an additional concurrent write of one word and a read of a different word for the array.

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Somers, NY, United States of America

Eugene S Schlig