Mstar Semiconductor, Inc.

U-blox Ag

Mstar France Sas

Mstar Software R&d, Ltd.

Eugène Pascal Herczog

A monitoring apparatus () for a network of communications-enabled devices includes: a processing resource () arranged to support a data selection module () and a data analysis module (). The apparatus () also includes a communications interface () operably coupled to the processing resource () and arranged to receive a plurality of data fragments. The plurality of data fragments each bear a respective device identifier and associated observation data, the plurality of data fragments respectively including a plurality of unique device identifiers. The data selection module () is arranged to read the respective identifiers of the plurality of data fragments and the associated observation data and to identify a set of the plurality of data fragments generated as a result of a common device characteristic. The data analysis module () is arranged to analyse the set of the plurality of data fragments identified by the data selection module in order to detect anomalous device activity.

Monitoring apparatus, device monitoring system and method of monitoring a plurality of networked devices

An interrupt controller () is adapted to control the execution of interrupt requests () of differing criticality by a processor () which is required to execute tasks () of differing criticality under the control of a computer operating system (); the interrupt controller being adapted to recognize critical () and non-critical () interrupt requests originating from different interrupt sources, and to recognize when the processor () is required to execute each of critical () and non-critical tasks (); the interrupt controller being further adapted to pass critical interrupt requests () to the processor () for execution in preference to non-critical interrupt requests (), to block non-critical interrupt requests () to the processor when they coexist with critical interrupt requests () or the processor () is required to execute critical tasks (), and to pass non-critical interrupt requests () to the processor () when they do not coexist with any critical interrupt requests () and the processor () has no critical tasks () to be executed. The interrupt controller () is preferably implemented in hardware and its operation is transparent to the processor ().

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Cambridge, United Kingdom

Eugène Pascal Herczog