Recogni Inc.

Mperpetuo, Inc.

Carl Zeiss Ag

Persimmons, Inc.

Eugene M Feinberg

Shabarivas Abhiram

Eran Steinberg

Ashwini Choudhary

Gary S Goldman

Jian Hui Huang

Berend Ozceri

Martin Stefan Patz

James Michael Bodwin

Pradeep R Joginipally

Gilles J C A Backhus

Robert F Young

Gary Gitelson

Hideaki Oshima

In a low power hardware architecture for handling accumulation overflows in a convolver unit, an accumulator of the convolver unit computes a running total by successively summing dot products from a dot product computation module during an accumulation cycle. In response to the running total overflowing the maximum or minimum value of a data storage element, the accumulator transmits an overflow indicator to a controller and sets its output equal to a positive or negative overflow value. In turn, the controller disables the dot product computation module by clock gating, clamping one of its inputs to zero and/or holding its inputs to constant values. At the end of the accumulation cycle, the output of the accumulator is sampled. In response to a clear signal being asserted, the dot product computation module is enabled, and the running total is set to zero for the start of the next accumulation cycle.

Low power hardware architecture for handling accumulation overflows in a convolution operation

Dynamic data quantization may be applied to minimize the power consumption of a system that implements a convolutional neural network (CNN). Under such a quantization scheme, a quantized representation of a 3×3 array of m-bit activation values may include 9 n-bit mantissa values and one exponent shared between the n-bit mantissa values (n<m); and a quantized representation of a 3×3 kernel with p-bit parameter values may include 9 q-bit mantissa values and one exponent shared between the q-bit mantissa values (q<p). Convolution of the kernel with the activation data may include computing a dot product of the 9 n-bit mantissa values with the 9 q-bit mantissa values, and summing the shared exponents. In a CNN with multiple kernels, multiple computing units (each corresponding to one of the kernels) may receive the quantized representation of the 3×3 array of m-bit activation values from the same quantization-alignment module.

Low power hardware architecture for a convolutional neural network

A first and second host device are configured to communicate data via a data channel (e.g., a half-duplex channel). A control channel (e.g., a full-duplex channel) may be used to arbitrate the dynamic assignment of the respective roles of master and slave to the first and second host devices. The arbitration procedure may include transmitting a first message from the first host device to the second host device that specifies information for allocating one or more time slots to the first host device, and transmitting a second message from the second host device to the first host device that specifies information for allocating one or more time slots to the second host device. At each of the first and second host devices, a communication schedule for the data channel may be determined based on a rule set, the first message and the second message.

Methods for arbitrating the role of bus master among a plurality of host devices

Contiguous columns of a convolutional engine are partitioned into two or more groups. Each group of columns may be used to process input data. Filter weights assigned to one group may be distinct from filter weights assigned to another group.

Methods for processing data in an efficient convolutional engine with partitioned columns of convolver units

A convolutional engine is configured to process input data that is organized into horizontal stripes. The number of accumulators present in each convolver unit of the convolutional engine may equal a total number of rows of data in each of the horizontal stripes.

Methods for processing horizontal stripes of data in an efficient convolutional engine

A convolutional engine is configured to process input data that is organized into vertical stripes.

Methods for processing vertical stripes of data in an efficient convolutional engine

A hardware architecture for implementing a convolutional neural network. Certain ones of the convolver units may be controlled to be active and others may be controlled to be non-active by a controller in order to perform convolution with a striding of greater than or equal to two.

Efficient convolutional engine

A hardware architecture for implementing a convolutional neural network.

A method for instantiating a convolutional neural network on a computing system. The convolutional neural network includes a plurality of layers, and instantiating the convolutional neural network includes training the convolutional neural network using a first loss function until a first classification accuracy is reached, clustering a set of F&#xd7;K kernels of the first layer into a set of C clusters, training the convolutional neural network using a second loss function until a second classification accuracy is reached, creating a dictionary which maps each of a number of centroids to a corresponding centroid identifier, quantizing and compressing F filters of the first layer, storing F quantized and compressed filters of the first layer in a memory of the computing system, storing F biases of the first layer in the memory, and classifying data received by the convolutional neural network.

Cluster compression for compressing weights in neural networks

Hibernating an android device includes freezing one or more tasks, processes, drives, data and/or files of open applications, or other RAM data, and creating a hibernation image. A resume image is generated based on the hibernation image. The resume image is stored to disk along with one or more hibernation parameters that are configured to guide Linux to specific memory locations of certain resume image data. Power to both the processor and the RAM storage devices of the android device are then cut off.

Efficient hibernation apparatus and method for digital devices

Labeled data is deterministically generated for training or validating machine learning models for image analysis. Approaches are described that allow this training data to be generated, for example, in real-time, and in response to the conditions at the location where images are generated by image sensors.

Deterministic labeled data generation and artificial intelligence training pipeline

A three-dimensional model of the environment of one or more camera devices is determined, in which image processing for inferring the model may be performed at the one or more camera devices.

Three-dimensional environment modeling based on a multi-camera convolver system

A digital camera includes an optical assembly and image sensor for capturing still and/or video images and displaying the images on a screen. The camera includes a touch slider that is configured for sensing a relative movement of a finger, thumb or stylus or other tool of a user, or combinations thereof, and adjusting a value of an imaging parameter based on the relative movement.

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San Jose, CA, United States of America

Eugene M Feinberg