Digital Equipment Corporation

Eugene L Yu

Paul J Natusch

David C Senerchia

James B Keller

Robert E Stewart

John F Henry, Jr, Deceased

A main memory unit for a data processing system has at least one memory board and allows each memory board to process data simultaneously. Each memory board may also include a plurality of memory array units which also can process data simultaneously. The main memory unit includes a memory interface unit, at least one memory board, and a memory unit bus for transferring address, data, command, and memory status signals between the memory boards and the memory interface unit.

Apparatus and method for providing distributed control in a main memory

For use in a data processing system, a main memory subsystem includes a plurality of memory boards for storing groups of logic signals. Each memory board includes an plurality of array units. Each array unit is adapted to store a group of logic signals that is equivalent in size to the field of data logic signals transferred on the system bus and has an address structure so that each addressable data signal group can be stored in a single array. The address field of each array unit is further adapted so that the probability of interfering activity in each array is low. The arrays are adapted process data signal groups independently, thus, activity involving several arrays can take place simultaneously. The memory subsystem is structured to provide a pipeline types of overlapping activity so that activity involving several array units can be in progress simultaneously. Because the manipulation of the storage cells requires the most amounts of time in the memory unit, and because the arrays are performing this activity independently for each signal group, then the memory unit can be adapted to process the signal groups applied sequentially to the system without delay in nonexceptional circumstances, the most general exceptional circumstance being the masked write operation.

Apparatus and method for providing distribution control in a main memory

In a data processing system in which access to a second unit by a first unit through a system bus is determined by an arbitration unit, when a requesting unit that receives access to the system bus is unable to use that access for interaction with the second unit, a busy signal is provided to the arbitration unit and to the units. The busy signal causes the units to reinstitute a request for access to the system bus when the subsystem had an aborted transaction. The busy signal enforces a delay in the next arbitration for the system bus until a unit, with an aborted transaction as a result of the busy signal, can reassert the request for access signal. Moreover, apparatus can be included with the arbitration unit that permits rearbitrating access to the bus using the priority conditions in effect at the time of the original arbitration.

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Groton, MA, United States of America

Eugene L Yu