Transwitch Corporation

Siemens Telecommunication Systems Ltd.

Eugene L Parrella

Subhash Chandra Roy

Paul Hembrook

Richard Mariano

Daniel C Upp

William G Bartholomay

Timothy M Shanley

Desikan V Srinivasan

Ian Ramsden

Mikio S Ichiba

Thomas M Preston

Sin-Min Chang

An apparatus for avoiding head of line blocking in an ATM device includes a scheduler, at least one multicast queue, at least one unicast queue, a multicast session table, a multicast timer, and a problem PHY vector. The methods of the invention include alternate scheduling between multicast queue(s) and unicast queue(s). If a PHY device in a multicast session is inactive, it is skipped and the next PHY in the session is serviced. When the session has serviced all of the active PHYs and there remain only inactive PHYs in the session table, the session is ended. Preferably, a timer is started when only inactive PHYs remain in a session and the session is ended when the timer expires, if not sooner. Preferably, a problem PHY vector is maintained and updated at the end of each multicast session and when PHYs become active. The problem PHY vector includes a list of all of the presently inactive PHYs. The multicast session is preferably ended when the only PHYs remaining in the session are listed in the problem PHY vector.

Method and apparatus for avoiding head of line blocking in an ATM (asynchronous transfer mode) device

A debugging interface includes a pair of decoders and an event history buffer coupled to the sequencer of a processor. The first decoder is coupled to the program counter of the sequencer and the Instruction RAM of the processor. The second decoder is coupled to the cause register of the sequencer and the event history buffer is also coupled to the cause register. The first decoder provides a three bit real time output which is indicative of the processor activity on a cycle by cycle basis. The three bit output indicates seven different conditions: whether the last instruction executed by the processor was an inc, an exception, an exception with no event history buffer entry, or a branch taken, whether there has been no instruction executed since the last clock cycle, and whether a jump was an immediate jump or a jump to a register. The event history buffer is loaded with more detailed information about the instruction last executed when the first decoder indicates that the last instruction was an exception or a jump to a register, and when there is a change in state of an interrupt line or an internal processor exception. An exemplary implementation of the debugging interface is embodied on an ASIC chip having three processors. Each processor is provided with a first and second decoders and a single event history buffer for all processors is provided on the chip.

Real time debugger interface for embedded systems

Methods for managing multiple queues of ATM cells in shared RAM while efficiently supporting multicasting include providing a common memory for storing ATM cells and for storing at least one pointer to each ATM cell stored, providing a management memory for storing an index to the pointers stored in common memory, a table for each multicast session, and an index to the free space in common memory. According to the presently preferred method, cells entering the switch are examined, placed in shared RAM, and a pointer to the RAM location is written in another location in the shared RAM. Table entries in management RAM are updated each time a cell is added to a queue. When a multicast session is begun, a multicast table is created with all of the addresses in the multicast session. When a multicast cell is received, the multicast session table is consulted and pointers to the cell are copied to queues for each address in the table. When a pointer exits a queue, the cell pointed to by the pointer is read and transmitted to the address of the queue. As the cell is read, the destination count for the cell is decremented. When the destination count is reduced to zero, the RAM location used to store the cell is added to the free list. Each time a pointer is read, the table entry for the affected queue is updated. When the queue becomes empty, an active bit in the table entry is toggled.

Method and apparatus for managing multiple ATM cell queues

An ATM switch system has a plurality of input ports and output ports all having associated buffers, and a source traffic control system which includes a shared bus coupling the ports, and a switch controller or arbiter which controls the transfer of data among the ports via the shared bus. ATM cells placed on the shared bus include an internal destination address which designates the output port within the switch to which the ATM cell is destined. The switch controller monitors the internal destination addresses of the ATM cells, and increments a counter associated with the destination port when the destination corresponds, and decrements other counters which do not correspond to the destination. Accordingly, bursts for a particular output port causes the count of the associated counter to grow large; whereas frequent or long breaks cause the count to drop. The counts are compared to a high threshold which alerts the arbiter that the buffer of the output port being tracked is in danger of overflowing. Upon receiving the alert, the arbiter either stalls the bus by refusing to grant access to the bus until the counter decrements below the first threshold, or grants bus access to the input port associated with the output port on the theory that the input port will not be sending data to its own output. A low threshold is utilized to declare that a burst is over and to free the counter for tracking a new burst to the same or a different output port.

Apparatus and method for limiting data bursts in ATM switch utilizing shared bus

A RISC processor includes a sequencer, a register ALU (RALU), data RAM, and a coprocessor interface. The sequencer includes an N.times.32 bit instruction RAM which is booted from external memory through the coprocessor interface. The RALU includes a four port register file for storage of three contexts, and an ALU. The ISA (instruction set architecture) according to the invention supports up to eight coprocessors. An important feature of the invention is that multiple sets of general purpose registers are provided for the storing of several contexts. According to a presently preferred embodiment, three sets of general purpose registers are provided as part of the RALU and a new opcode is provided for switching among the sets of general purpose registers. With multiple sets of general purpose registers, context switching can be completed in three processing cycles. In addition, one set of general purpose registers can be loaded by a coprocessor while another set of general purpose registers is in use by the ALU. According to a presently preferred embodiment, each of the three sets of general purpose registers includes twenty-eight thirty-two bit registers. In addition, according to the presently preferred embodiment, a single set of four thirty-two bit registers is provided for use in any context. The set of common registers is used to store information which is used by more than one context.

RISC processor architecture with high performance context switching in

A synchronizer for telecommunications signals includes a telecommunications interface for receiving bits of a telecommunications signal having a frame, an SRAM which stores bit-defined states for a plurality of bit locations in the frame, a state update lookup table for changing the states for a plurality of the frame bit locations of the SRAM based on a previous state and based on an incoming bit of the telecommunications signal, and frame location identification logic for determining the location of the overhead bit of the telecommunications signal frame based on the states of the plurality of bit locations. In a first embodiment, the SRAM is an x by y bit SRAM, where x equals the number of bits in the frame, and y is large enough so that the number of possible states .ltoreq.2.sup.Y. In a second embodiment, the bit locations are divided into a plurality of subgroups or stages, and the SRAM is at least an Int (x/s) by y bit SRAM, where s is an integer greater than one which represents the number of stages of the state machine, and Int (x/s) is the quotient x/s rounded up. In the second embodiment, after the state of a bit location in a first stage reaches a predetermined value, the bits of an associated frame location are used for state updates in a second stage.

Telecommunications framer utilizing state machine

Circuit board insertion circuitry is used in conjunction with a staggered electrical connector. The insertion circuitry includes an isolated circuit which receives a high system voltage upon first stage contact between the card and a high voltage bus, and uses that high system voltage to tristate the output of a transceiver on the circuit board prior to second stage contact being made between the transceiver and the backplane data bus. Override circuitry for overriding the tristating effects of the isolating circuit are provided such that when the bias circuit which controls the transceiver output is properly powered, the bias circuit will control the transceiver output, and not the isolated circuit. Additional circuitry which isolates the circuit board so that a power fault on the board will not impact other boards on the backplane is also provided. The additional circuitry preferably includes a relative large resistor and a Schottky diode which are provided in parallel between a 5 V bus and the protection diodes of the transceiver.

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Monroe, CT, United States of America

Eugene L Parrella