Sandisk Technologies Inc.

Silicon Storage Technology, Inc.

Eugene Jinglun Tam

Thuan Vu

Xian Liu

Jack Frayer

Alexander Kotov

Michael James Heinz

Tho Ngoc Dang

Jung Hee Yun

Michael K Doan

Yan Li

Bo Liu

Kwang-Ho Kim

Chi-Ming Wang

Alexander Kwok-Tung Mak

Pao-Ling Koh

Cuong Quoc Trinh

Rohan Patel

A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes. The modes include a pass-through mode, where the main portions of the memory circuit are inactive and commands and data are passed through to other devices in the tree structure, and an active mode, where the main portions of the memory circuit are active and can receive and supply data. Reverse active and reverse pass-through modes, where data flows in the other direction, can also be used. The pads of the memory chip can be configurable to swap input and output pads to more efficiently form the memory chips into a package.

Packaging of high performance system topology for NAND memory systems

A topology for memory circuits of a non-volatile memory system reduces capacitive loading. For a given channel, a single memory chip can be connected to the controller, but is in turn connected to multiple other memory devices that fan out in a tree-like structure, which can also fan back in to a single memory device. In addition to the usual circuitry, such as a memory arrays and associated peripheral circuitry, the memory chip also includes a flip-flop circuit and can function in several modes, including pass-through and active modes. Techniques are presented for the addressing of memory chips within such a topology, including an address assignment scheme.

Addressing auto address assignment and auto-routing in NAND memory network

High performance system topology for NAND memory systems

An efficient wide range bit counter is presented that can support a wide range of counts with scientific notation. The counting scheme is dynamically altered to maintain a balance between accuracy and performance and allows early termination to fit timing budgets. Two (or more) counters each track the number of occurrences of a corresponding subset of events, where, when none of the counters have reached their capacities, the total count is the sum of the counts for the subsets. If one of the counters reaches it capacity, the other counter is then used as an extension of this first counter and the total count is obtained by scaling the count of the extended counter. In case of early termination, the accumulated count can be compensated to approximate the full count.

Efficient wide range bit counter

A delay and calibration circuit for an input/output determines an appropriate delay by trying a range of different delays, and for each delay, determining the number of times that a given data sequence is accurately received. The data sequence may be a command, address, host data, or other data. Appropriate delays may be found for different temperatures.

Auto-calibration for high speed input/output

Techniques are presented to detect word line failures (such as word line to word line shorts, control gate to substrate shorts, broken word lines, and so on) in non-volatile memory arrays. A first simultaneous read of multiple word lines is performed, followed by a second simultaneous read of the same word lines, where the read conditions of the two reads are shifted by a margin. For example, one of the read could use a standard read voltage on the word lines, while the other read could shift these levels slightly higher. The results of the two reads can then be compared on a bit line by bit line basis, XOR-ing the results to determine is the set of word lines may include any defective members.

Multi-word line erratic programming detection

Techniques are disclosed herein for determining whether there is a defect that occurred as a result of programming non-volatile storage elements. Example defects include: broken word lines, control gate to substrate shorts, word line to word line shorts, double writes, etc. The memory cells may be programmed such that there will be a substantially even distribution of the memory cells in different data states. After programming, the memory cells are sensed at one or more reference levels. Two sub-groups of memory cells are strategically formed based on the sensing to enable detection of defects in a simple and efficient manner. The sub-groups may have a certain degree of separation of the data states to avoid missing a defect. The number of memory cells in one sub-group is compared with the other. If there is a significant imbalance between the two sub-groups, then a defect is detected.

Asymmetric state detection for non-volatile storage

Techniques are presented for dealing with errors that arise from cluster fails, where a number of memory cells in the same area fail. An ECC code word can tolerate a given total amount of error while still being able to still be decoded, so that if error due to clusters can be identified and removed or lessened, it may be possible to still decode the word not otherwise decodable. After identifying possible error bit cluster locations, one or more bits in the cluster locations are flipped to see if the data content of the code word can be extracted. For embodiments using LDPC ECC code, uncertainty can be added for the bits of a suspected cluster location. To reduce the effects of cluster failures, code words can be interleaved within a page and the difference code words can have differing levels of ECC capability.

Data recovery on cluster failures and ECC enhancements with code word interleaving

Methods and devices for recovering data stored in a non-volatile storage device are provided. Data may be recovered for memory cells associated with a word line that cannot be read using ECC that was calculated based on the data stored on that word line. This allows recovery for situations such as a word line shorting to the substrate or two adjacent word lines shorting together. When programming memory cells associated with a group of word lines, parity bits may be calculated and stored in memory cells associated with an additional word line in the memory device. When reading memory cells associated with one of the word lines in the group, an otherwise unrecoverable error may occur. By knowing which word line is defective, its data may be recovered using the parity bits and the data of all of the other word lines in the group.

On chip data recovery for non-volatile storage

A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells.

Non-volatile memory device with plural reference cells, and method of setting the reference cells

A power supply voltage for a memory chip is compared with a plurality of threshold voltages that correspond to voltages below which classes of memory operations can no longer be guaranteed. When the power supply voltage drops below a threshold voltage, appropriate action is taken, which may include generating an indicator such as a flag, proceeding with the operations in some modified manner, or disabling operations that are no longer guaranteed, either permanently or until power is restored, or until some other appropriate time.

Growing community of inventors

Saratoga, CA, United States of America

Eugene Jinglun Tam