International Business Machines Corporation

Eugene James Nosowicz

David Jia Chen

Roger Paul Gregor

Robert Charles Pearson

Eric Lee Carter

A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes an Llatch and an Llatch coupled to the Llatch. Data is first latched in the Llatch during a first half clock cycle and then latched in the Llatch during a second half clock cycle. A path opposite a latched data state is gated off in both the Llatch and the Llatch, where a path to a voltage supply rail is gated off with a latched low data state and a path to ground is gated off with a latched high data state.

Set/reset latch with minimum single event upset

A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes any L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in the L2 latch during a second half clock cycle. A path opposite a latched data state is gated off in both the L1 latch and the L2 latch, where a path to a voltage supply rail is gated off with a latched low data state and a path to ground is gated off with a latched high data state.

A method and apparatus are provided for implementing a fault tolerant phase locked loop (PLL). The PLL circuit includes a divide by N circuit defined by a plurality of sub-divide by N functions, each providing a feedback frequency signal applied to a voter circuit. The voter circuit provides an output feedback frequency signal based upon a majority vote of the sub-divide by N functions.

Method and apparatus for implementing fault tolerant phase locked loop (PLL)

A method and latch circuit for implementing enhanced performance includes critical data and clock paths and non-critical sections. A low voltage threshold (LVT) transistor is used only in the critical data and clock paths. The non-critical sections are implemented with regular VT, (RVT), or low leakage (LLD) transistors. The latch circuit advantageously is implemented using LVT devices in the internal critical paths of the latch and RVT output buffer transistors.

Method and latch circuit for implementing enhanced performance with reduced quiescent power dissipation using mixed threshold CMOS devices

A data storage element for use in LSSD compliant circuit designs. The data storage element has an alternate, or scan, data input circuit that has increased immunity to electrical noise while maintaining lower power consumption than the circuits used for primary data input. This increased noise immunity reduces the probably that noise on the alternate data input will cause an unintended change of data state stored in the data storage element. Modification of latch circuits used in the data storage element allow a reduction in the number of transistors used in the latch circuits, thereby compensating for the increase in transistors used in the alternate data input circuit and allowing the data storage element to use the same number of transistors as prior designs that have less noise immunity on their alternate data inputs.

Low power data storage element with enhanced noise margin

A pulse generation circuit delivers an output pulse whose width is tailored to the load. The pulse generation circuit comprises the following components. A drive circuit has an input coupled to receive a clock signal and an output coupled to drive a load. A comparator has an input coupled to the output of the drive circuit. Another input of the comparator is supplied by a reference voltage. A feedback circuit comprises logic gates and is coupled between the output of the comparator and the input of the drive circuit. The feedback circuit terminates a pulse output from the drive circuit when the pulse voltage output from the drive circuit exceeds the reference voltage. The reference voltage is higher than a voltage required to trigger the logic gates and a voltage required to drive the load. This ensures that the load is driven adequately over a wide range of load currents and capacitances. By setting the reference voltage between the voltage required to drive the load and the supply voltage, the pulse width is not excessive.

Pulse generator with controlled output characteristics

An improved polarity hold latch is described having a set and reset capability integrated therein. As implemented, this latch provides the desired logical functions at a reduced circuit cost and power requirements. At the same time, it overcomes the need to test for and resolve potential signal race conditions. The improved latch is particularly susceptible of being implemented on a single chip.

Cascode polarity hold latch having integrated set/reset capability

Apparatus for assembling binary data bits in parallel by groups in variable, selected locations in a shift register for subsequent serial readout. One or more shift registers are arranged in a matrix of rows and columns of storage cells and addressed along one coordinate while a plurality of data are applied in parallel along the orthogonal. Selector circuits are controlled to selectively shift a data word to enable the first bit in the word to be stored in any storage position within the addressed coordinate, with each remaining bit in the word stored in a correspondingly contiguous storage position in the matrix. Bit storage cells of the shift registers are of the set-reset latch type so that once set they cannot be changed by subsequent data bits until the entire array is reset. This enables the overwriting of successive data bytes.

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Vestal, NY, United States of America

Eugene James Nosowicz