Teradyne, Inc.

Zehntel, Inc.

Eugene H Breniman

Douglas W Raymond

B Karen McElfresh

Barbara K McElfresh

A minimal memory in-circuit digital tester with vector memory concentrated in a centralized vector processor circuit, eliminating the need for pin memory. The vector processor circuit memory is partitioned into two blocks, a pointer memory and a change list memory. Every vector clock cycle has one pointer memory entry. The pointer memory entry is an address for the change list memory. The change list memory contains lists of nodes used in the vector test sequence. Each change list entry contains a pin number and several control bits. The control bits define functions such as whether the pin will toggle its data or enable state, whether there are more pins in that particular change list, and whether the list or test has ended. When the end of each change list is reached, all pins that have been primed by that change list will be toggled. The next entry of the pointer memory is then selected which, in turn, selects another, or perhaps the same change list in the change list memory. Each vector within a test vector file corresponds to one entry in the pointer memory, however, several different pointers can address the same change list. As a result, test vector files of great length can be accommodated using minimal memory.

Method and apparatus for a minimal memory in-circuit digital tester

A digital in-circuit tester has a test-head controller which controls bursts of test vectors generated by a group of driver-receiver channels, the group of driver-receiver channels responsive to an erase instruction from test-head controller. At least one driver-receiver channel is adapted for nullifying the action of an erase instruction. The driver-receiver channel has a first memory for storing information which determines certain actions of the channel during the next burst of test vectors. The memory is responsive to the erase instruction for being erased. The driver-receiver channel also has an erase inhibitor including: an inhibition-state-retention means responsive to an erase-inhibit instruction from the test-head controller for storing an erase-inhibit logic state; and a combinatorial means communicatively coupled to the inhibition-state-retention means, and responsive to the stored erase-inhibit logic state from the inhibition-state-retention means, and responsive to the test-head controller erase instruction for nullifying the action of the erase instruction.

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Antioch, CA, United States of America

Eugene H Breniman