Intel Corporation

Apple Inc.

Eugene Gorbatov

Andrew D Henroid

Eliezer Weissmann

Paul S Diefenbaugh

Russell Jerome Fenger

Gaurav Khanna

Avinash N Ananthakrishnan

Dheeraj R Subbareddy

David A Koufaty

Krishnakanth Venkata Sistla

Alon Naveh

Ankush Varma

James G Hermerding, Ii

Ganapati Srinivasa

Scott D Hahn

Paolo L Narvaez

Barnes Cooper

Mishali Naik

Paul Brett

Andrew J Herdrich

Inder M Sodhi

Guy M Therien

Ulf Hanebutte

Vasudevan Srinivasan

Howard S David

Alexander Uan-Zo-Li

Chee Lim Nge

Rajesh P Banginwar

Efraim Rotem

Stephen H Gunther

Eric C Samson

David W Browning

Michael Mishaeli

Neil W Songer

Rajshree Chabukswar

Zhongsheng Wang

Hongzhong Zheng

Bret L Toll

Jason W Brandt

Ravishankar Iyer

Christopher B Wilkerson

Rahul Khanna

Stephen Anthony Fischer

Alaa R Alameldeen

Zeshan A Chishti

Ashish V Choubal

Chia-Hung Sophia Kuo

Hisham Shafi

Rinat Rappoport

Nithyananda Siva Jeganathan

Nikhil Gupta

Nagabhushan Chitlur

Yifan Li

Basavaraj B Astekar

Tin-Cheung Kung

Vincent J Zimmer

Rajesh Poornachandran

Vedvyas Shanbhogue

Ronny Ronen

Robert Charles Swanson

Atsuo Kuwahara

Boris Ginzburg

Jr-Shian Tsai

Kristoffer Fleming

John H Crawford

Ashok Raj

Vivek Garg

Robert E Gough

Bryant E Bigbee

Sarathy Jayakumar

Mingqiu Sun

Harish Krishnamurthy

Jiewen Yao

John S Howard

Tod F Schiff

Ahmad Yasin

James W Alexander

Anil Aggarwal

Anil K Kumar

Richard J Greco

Julius Yuli Mandelblat

Tomm Aldridge

Michael Zelikson

Aamer Jaleel

Alexander Lyakhov

Pavan Kumar

Gopinatth Selvaraje

Hisham Abu Salah

Yuval Yosef

Sameer Shekhar

Ralph Hasholzner

Eric K Mann

Suneeta Sah

Ajay G Gupta

Ahmad A Samih

Tong Li

Kenan Kocagoez

Philip R Lehwalder

Arik Gihon

Annabelle Pratt

In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.

System, apparatus and method for providing hardware state feedback to an operating system in a heterogeneous processor

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.

Apparatus and method for dynamic control of microprocessor configuration

Embodiments are generally directed to enhanced power management for support of priority system events. An embodiment of a system includes a processing element; a memory including a registry for information regarding one or more system events that are designated as priority events; a mechanism to track operation of events that requires Turbo mode operation for execution; and a power control unit to implement a power management algorithm. The system is to maintain an first energy budget and a second residual energy budget for operation in a Turbo power mode, and wherein the power management algorithm is to determine whether to authorize execution of a detected system event in the Turbo power mode based on the second residual energy budget upon determining that the first energy budget is not sufficient for execution of the detected system event and that the detected system event is designated as a priority event. Priority designations for the priority events may include a first High Priority designation and a second Critical designation.

Enhanced power management for support of priority system events

The present disclosure is directed to dynamically prioritizing, selecting or ordering a plurality threads for execution by processor circuitry based on a quality of service and/or class of service value/indicia assigned to the thread by an operating system executed by the processor circuitry. As threads are executed by processor circuitry, the operating system dynamically updates/associates respective class of service data with each of the plurality of threads. The current quality of service/class of service data assigned to the thread by the operating system is stored in a manufacturer specific register (MSR) associated with the respective thread. Selection circuitry polls the MSRs on a periodic, aperiodic, intermittent, continuous, or event-driven basis and determines an execution sequence based on the current class of service value associated with each of the plurality of threads.

Operating system assisted prioritized thread execution

A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.

Technology for optimizing hybrid processor utilization

Peak power setting circuitry is provided to set a peak power value for an integrated circuit device. A power supply interface is to receive a value to estimate a peak power capacity of a power supply serving the integrated circuit device and processing circuitry is provided to calculate an approximate peak power for the integrated circuit device. A peak power for the integrated circuit device is determined by increasing the approximate peak power depending on an amount by which the integrated circuit device power is reduced in response to assertion of a throttling signal.

Peak power determination for an integrated circuit device

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of logical processors including comprising one or more of a first logical processor type and a second logical processor type, the first logical processor type associated with a first core type and the second logical processor type associated with a second core type; a scheduler to schedule a plurality of threads for execution on the plurality of logical processors in accordance with performance data associated with the plurality of threads; wherein if the performance data indicates that a new thread should be executed on a logical processor of the first logical processor type, but all logical processors of the first logical processor type are busy, the scheduler to determine whether to migrate a second thread from the logical processors of the first logical processor type to a logical processor of the second logical processor type based on an evaluation of first and second performance values associated with execution of the first thread on the first or second logical processor types, respectively, and further based on an evaluation of third and fourth performance values associated with execution of the second thread on the first or second logical processor types, respectively.

Apparatus and method for adaptively scheduling work on heterogeneous processing resources

A power supply architecture combines the benefits of a traditional single stage power delivery, when there are no additional power losses in the integrated VR with low VID and low CPU losses of FIVR (fully integrated voltage regulator) and D-LVR (digital linear voltage regulator). The D-LVR is not in series with the main power flow, but in parallel. By placing the digital-LVR in parallel to a primary VR (e.g., motherboard VR), the CPU VID is lowered and the processor core power consumption is lowered. The power supply architecture reduces the guard band for input power supply level, thereby reducing the overall power consumption because the motherboard VR specifications can be relaxed, saving cost and power. The power supply architecture drastically increases the CPU performance at a small extra cost for the silicon and low complexity of tuning.

Digital linear regulator clamping method and apparatus

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores; wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core, wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.

When power is provided through a USB-C cable from a source device to a sink device, a sudden connection or disconnection of the cable between the two devices may cause a sudden power surge or power drop in at least one of those devices, leading to other problems. To avoid this sudden event from causing potential damage or disruption to one of the devices, in some embodiments a CC pin in the cable is used to announce the impending connection/disconnection, and the device may throttle back its power consumption before power is actually applied to or removed from the power pins.

USB type-C power delivery management

Methods and devices for allocating power among a plurality of circuits in a communication device, including determining a power budget for allocating to the plurality of circuits from a power supply information; receiving an activity status from a first circuit of the plurality of circuits; determining a first power value based on the activity status; deriving a second power value based on the first power value and the power budget; and allocating power to one or more remaining circuits of the plurality of circuits based on the second power value.

Devices and methods for power allocation

In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.

Supercapacitor-based power supply protection for multi-node systems

In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.

Techniques and system for managing activity in multicomponent platform

Growing community of inventors

Hillsboro, OR, United States of America

Eugene Gorbatov