Texas Instruments Corporation

Memc Electronic Materials, Inc.

Eugene C Davis

Alexei Sadovnikov

Pushpa Mahalingam

Umamaheswari Aghoram

Gul Bahar Basim

Binghua Hu

Abbas Ali

Rajni J Aggarwal

Steven J Adler

Lawrence D Dyer

Jonathan Philip Davis

Sopa Chevacharoenkul

John Britton Robbins

Jerry B Medders

Shariq Arshad

Damien Thomas Gilmore

Jerry D Smith

Franklin L Allen

Vikki S Simpson

Prakash Dalpatbhai Dev

Azghar H Khazi-Syed

Khanh Quang Le

Serkan Kincal

Yi-yang Zhou

Michael Cunningham

Sarah Elizabeth Bradshaw

Jonathan Roy Garrett

Kaneez Eshaher Banu

An electronic device comprises a semiconductor substrate including majority carrier dopants of a first conductivity type, a semiconductor surface layer including majority carrier dopants of a second conductivity type, field oxide that extends on the semiconductor surface layer, and an isolation structure. The isolation structure includes a trench that extends through the semiconductor surface layer and into one of the semiconductor substrate and a buried layer of the semiconductor substrate, and polysilicon including majority carrier dopants of the second conductivity type, the polysilicon fills the trench to a side of the semiconductor surface layer.

Deep trench isolation with field oxide

A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.

Method of reducing voids and seams in trench structures by forming semi-amorphous polysilicon

A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure located between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon oxide.

LDMOS with high-k drain STI dielectric

A laterally diffused metal oxide silicon (LDMOS) transistor and a method of making the LDMOS transistor are disclosed. The LDMOS transistor includes a drain drift region formed in a substrate and containing a drain contact region. A gate structure overlies a channel region in the substrate and a first shallow-trench isolation (STI) structure is formed between the drain contact region and the channel region. The first STI structure contains a high-k dielectric and a second STI structure contains silicon dioxide.

Soil setting gardening implement

Flexible carrier sling

Gardening implement

A one-step CMP process for polishing three or more layer film stacks on a wafer having a multilayer film stack thereon including a silicon nitride (SiNx) layer on its semiconductor surface, and a silicon oxide layer on the SiNx layer, wherein trench access vias extend through the silicon oxide layer and SiNx layer to trenches formed into the semiconductor surface, and wherein a polysilicon layer fills the trench access vias, fills the trenches, and is on the silicon oxide layer. CMP polishes the multilayer film stack with a slurry including slurry particles including at least one of silica and ceria. The CMP provides a removal rate (RR) for the polysilicon layer &#x3e; a RR for the silicon oxide layer &#x3e; a RR for the SiNx layer. The CMP process is continued to remove the polysilicon layer, silicon oxide layer and a portion of the SiNx layer to stop on the SiNx layer. Optical endpointing during CMP can provide a predetermined remaining thickness range for the SiNx layer.

Single step CMP for polishing three or more layer film stacks

A mechanical polishing apparatus includes a polishing pad, at least one carrier head positioned over and off center relative to the polishing pad and configured for holding at least one substrate against the polishing pad within a first annular region of the polishing pad when the polishing pad is rotating. At least one conditioning head is positionable over and off center relative the polishing pad at a plurality of first positions and configured for applying a contacting surface of at least one conditioning pad against the polishing pad when the polishing pad is rotating, where the conditioning pad is applied to a second annular region of the polishing pad and moves between the plurality of first positions. In the apparatus, the diameter of the conditioning pad&#x2266;a difference between a radius of the polishing pad and a width of the first annular region.

Polish pad conditioning in mechanical polishing systems

A method of conditioning a CMP polishing pad to attain a desired thickness profile in a polished layer on a wafer is disclosed. The incoming thickness profile of the layer to be polished, the thickness profile of the polishing pad, a polish rate of layer as a function of pressure and the removal rate of polishing pad material by a conditioning block are used to compute a sweep pattern for the conditioning block which will produce a desired thickness profile on the polishing pad. The method may be applied to maintaining the desired profile on the polishing pad during the course of polishing multiple wafers. The pad profile may be adjusted to keep pressure between the pad and the wafer to a safe limit to reduce polishing defects.

Predictive method to improve within wafer CMP uniformity through optimized pad conditioning

A pad shaping tool for shaping a polishing pad. The tool includes a disk having a first side and a second side and at least two discontinuous pad shaping surfaces located in spaced apart positions relative to each other on the first side of the disk. The pad shaping surfaces are simultaneously engageable with a polishing surface of the polishing pad for shaping the polishing surface as the pad rotates relative to the tool to change a cross sectional profile of the polishing surface from a curved shape to a flatter shape. A process for reconditioning the polishing pad on a rotatable platform of a wafer polishing machine includes the steps of engaging the pad shaping tool with the polishing surface of the pad such that at least two discontinuous pad shaping surfaces of the tool simultaneously engage the polishing surface, and rotating the polishing pad while preventing translational movement of the tool relative to the pad so that the tool shapes the polishing surface of the pad to be more nearly flat.

Process for reconditioning polishing pads

The protection to the backside of the semiconductor wafer is accomplished by applying a layer of silicon oxide or silicon nitride or other deposited material to the back surface of a semiconductor wafer to protect against particles, scratches, and etching by mild caustic solutions. The layer remains in place during all three processes, edge pre-polish, mirror edge polish, and wafer polish.

Method of surface protection of a semiconductor wafer during polishing

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McKinney, TX, United States of America

Eugene C Davis