International Business Machines Corporation

Eugene B Risi

Dan Peter Dumarot

Moon Jung Kim

Daeik Daniel Kim

Karl J Duvalsaint

Vincent V Diluoffo

This invention describes an apparatus, computer architecture, memory structure, memory control, and cache memory operation method for multi-core processor. A logic core bypasses immediate cache memory units with low yield or deadly performance. The core mounts (multiple) cache unit(s) that might already be in use by other logic cores. Selected cache memory units serve multiple logic cores with the same contents. The shared cache memory unit(s) serves all the mounting cores with cache search, hit, miss, and write back functions. The method recovers a logic core whose cache memory block is not operational by sharing cache memory blocks which might already engage other logic cores. The method is used to improve reliability and performance of the remaining system.

Cache memory bypass in a multi-core processor (MCP)

A method includes performing a boot up of a computer having a system on-chip having multiple processors and a nonvolatile read-only machine-readable medium. The boot up includes enabling a first processor of the multiple processors, while maintaining others of the multiple processors in a disabled state. The boot up includes retrieving initial stage instructions from the nonvolatile read-only machine-readable medium. The boot up also includes executing the initial stage instructions and validating multiple stages of firmware separately. The boot up includes, in response to validating the multiple stages of firmware, executing the multiple stages of firmware in consecutive stages of the boot up, wherein executing of each stage of the multiple stages of firmware enables a different set of disabled hardware components of the computer. The boot up also includes validating an operating system and, in response to validation, transferring control of the computer to the operating system.

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Essex Junction, VT, United States of America

Eugene B Risi