Qst Holdings LLC

Altera Corporation

Cornami, Inc.

Quicksilver Technology, Inc.

Nvidia Corporation

Sviral, Inc.

Qst Holding, LLC

Eugene B Hogenauer

Paul L Master

Walter James Scheuermann

W James Scheuermann

Ghobad Heidari

Kuor-Hsin Chang

Dan MingLun Chuang

Bicheng William Wu

W H Carl Ebeling

Bjorn Freeman Benson

Bjorn Freeman-Benson

A computing system with a plurality of nodes is disclosed. At least one of the plurality nodes includes an execution unit configured to execute an operation. An interconnection network is coupled to the plurality of nodes. The interconnection network is configured to provide interconnections among the plurality of nodes. A control node is coupled to the plurality of nodes via the network to manage the execution of the operation by the one or more of the plurality of nodes.

Control node for multi-core system

A hardware task manager for an adaptive computing system. The adaptive computing system includes a plurality of computing nodes including an execution unit configured to execute tasks. An interconnection network is operatively coupled to the plurality of computing nodes to provide interconnections among the plurality of computing nodes. The hardware task manager manages execution of the tasks by the execution unit.

Hardware task manager

The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

An apparatus for processing operations in an adaptive computing environment is provided. The adaptive computing environment including at least one processing node. A node includes a memory configured to receive and store data. The data is received from a programmable interconnection network and stored. The node also includes an execution unit configured to perform a signal processing operation. The operation is performed using data retrieved from the memory and an output result is generated. The output result may be used for further computations or sent directly to the programmable interconnection network for transfer to another processing node in the adaptive computing environment.

Arithmetic node including general digital signal processing functions for an adaptive computing machine

A hardware task manager for an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from tasks. Likewise, output buffers must also be available before the task can start to execute and store results. The hardware task manager maintains a counter associated with each buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and the buffer is not ready and the associated task cannot run. Predetermined numbers of bytes, or 'units,' are stored into the input buffer and an associated counter is incremented. When the counter value transitions from a negative value to a zero the high-order bit of the counter is cleared indicating the input buffer has sufficient data and is available to be processed.

Adaptive integrated circuitry with heterogenous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

A system acquisition module and corresponding method for facilitating PN code searching which has a PN sequence generator configurable to generate a plurality of PN sequences. The module and method also includes computational units configurable to correlate each received signal sample of a plurality of received signal samples with a corresponding PN sequence of the plurality of PN sequences, and further configurable to provide other hardware resources. A number of computational units from the plurality of computational units are selectively configured to correlate the received signal samples with the PN sequences&#x2014;the number depending upon availability of the plurality of computational units from providing the other hardware resources. In another embodiment, a communication device having a system acquisition function is provided which includes the system acquisition module and a receiver configured to receive signals, where a plurality of configurable computational units are selectively configurable to implement the PN sequence generator.

Apparatus, module, and method for implementing communications functions

Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements

A hardware task manager for managing operations in an adaptive computing system. The task manager indicates when input and output buffer resources are sufficient to allow a task to execute. The task can require an arbitrary number of input values from one or more other (or the same) tasks. Likewise, a number of output buffers must also be available before the task can start to execute and store results in the output buffers. The hardware task manager maintains a counter in association with each input and output buffer. For input buffers, a negative value for the counter means that there is no data in the buffer and, hence, the respective input buffer is not ready or available. Thus, the associated task can not run. Predetermined numbers of bytes, or 'units,' are stored into the input buffer and an associated counter is incremented. When the counter value transitions from a negative value to a zero the high-order bit of the counter is cleared, thereby indicating the input buffer has sufficient data and is available to be processed by a task.

The present invention provides an adaptive integrated circuit. The various embodiments include a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations.

A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit. The compiler generates the configuration information, from the scheduled algorithm and the selected adaptive computing circuit version, for the performance of the algorithm by the adaptive computing integrated circuit. In the exemplary embodiments, multiple versions of configuration information may be generated, for different circuit versions, different feature sets, different operating conditions, and different operating modes.

Growing community of inventors

San Carlos, CA, United States of America

Eugene B Hogenauer