Hewlett-packard Development Company, L.P.

Hewlett-packard Company

Agilent Technologies, Inc.

Eugene A Roylance

Robert D Morrison

James G Bearss

Arlin R Jones

Wayne E Bradburn

Shell Sterling Simpson

Kenneth Kay Smith

Robert A Rust

Terry M Nelson

Randall Edward Grohs

Rodolfo Jodra

George Henry Kerby

John Harris

Brad R Larson

Kenneth E Major

Marc L Warner

Mark W Maloney

A method comprising storing a first line of data that is received from processing circuitry across a first set of conductors prior to receiving a first signal from a laser engine having a plurality of laser units and providing the first line of data and a second line of data that is received from the processing circuitry across the first set of conductors to the laser engine in response to receiving the first signal is provided.

Providing data

An implementation of a technology, described herein, for efficient and flexible multi-bit halftoning on a marking device, such as a printer. At least one implementation of the technology, described herein, performs multi-bit halftoning with hardware (e.g., circuitry) rather than a programmable processor. Furthermore, at least one implementation performs multi-bit halftoning for a variable number of bits per pixel and a variable resolution. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

Efficient and flexible multi-bit halftoning

A method for adjusting a laser diode drive current pulse, comprises providing a power correction table comprising drive current pulse correction factors corresponding to counter positions. The method also comprises providing a jump table comprising counter position adjustments corresponding to correction factors. A count value of a position within the counter positions is maintained. Maintaining the count value comprises indexing the count value to the jump table and incrementing the count value for each of a series of pixel clocks. A correction factor is determined, wherein determining the current correction factor comprises indexing the count value to the power correction table.

Laser diode modulator and method of controlling laser diode modulator

A memory integrated into a removable cartridge for an image forming device is formatted to store a state variable reflecting a state of a printing component. A method embodiment includes reading the state variable. An image enhancement technique, selected according to the state variable, is implemented. In another embodiment, the memory contains technique selection criteria. The technique selection criteria is processed with the state variable to select a template set identifying one or more image enhancement techniques.

Methods and apparatus for selecting image enhancement techniques

An apparatus and system include means to identify first and second pixel toner densities associated with selected pixels included in a color plane window, and means to generate at least one modified color plane window having identifications assigned to the pixel toner densities for transmission to a monochrome enhancement module. An article contains instructions causing a machine to execute a method including selecting a plurality of original color plane windows, each having a number of pixels, associating each pixel in each of the windows with an identification of VALID or INVALID, generating a plurality of modified windows to correspond to the plurality of original windows, wherein each one of the plurality of modified windows includes the associated identifications, and transmitting the modified windows to a monochrome enhancement module.

Resolution enhancement apparatus, systems, and methods

The system, methods and hardware described herein relate to processing raster data on an EP (electrophotographic) process printing device. A hardware ASIC supports multiple EP print engine configurations through a common delay window block that presents a variable two-dimensional view of raster data formatted in a consistent manner that is compatible for processing by various enhancement blocks. Benefits of the disclosed system, methods and hardware include decreased development costs for EP printers due to a reduced need to design, test, and manufacture different ASICs for numerous EP print engine configurations.

Supporting multiple print engine configurations through compatible delay window storage modes

The present invention is a method and system for mixed resolution, multi-channel color image processing including compression, transmission and decompression. The color information is defined at a lower resolution since colors generally do not change at a high frequency and higher compression ratios may be obtained with the lower resolution. The edge information contains the commands switch between the foreground and background colors. The edge information occurs at high resolution and high frequency rates relative to the color information. The lower resolution color planes can be pixel replicated to the resolution of the edge information after compression and decompression for proper edge selection to occur. The resulting reconstructed image of foreground and background colors retains high detail.

Method and system for image processing including mixed resolution, multi-channel color compression, transmission and decompression

Lower resolution source data is synthesized to a higher resolution format for subsequent rendering on a lower resolution output device. Synthesis occurs by selecting or generating and using a synthesis template that represents a configuration of a plurality of pixel data in the higher resolution format into which the lower resolution source data is to be synthesized. A working or active pixel is identified from the lower resolution source data, a synthesis template is selected, and then the synthesis template pixel data is substituted for the working pixel for rendering on the output device. The synthesized higher resolution data is rendered in a manner such that dots represented by the synthesized data are formed interstitially relative to scan lines of the given lower raster/resolution capability of the output device. The working pixel is identified in the lower resolution data by recognizing a configuration of a plurality of pixel data adjacent the working pixel. The synthesis template comprises at least a two by two cell matrix for pixel placement in the higher resolution format. The synthesis template pixel placement is formed to provide an apparent merge of the pixel data in the higher resolution format with the adjacent pixel data of the lower resolution format data.

Programmable mapping of lower resolution digital data to a higher resolution for output on a lower resolution device

A pulse width modulator (PWM) circuit is provided. The PWM circuit includes a selective synchronization circuit configured to receive vector signals, and selectively synchronize the vector signals. The synchronized vector signals are provided to a tap selection circuit configured to output tap selection signals that are logically combined by a transition generating circuit to produce a pulse width modulated signal based on logically detected transitions in the tap selection signals.

Pulse with modulation signal generating methods and apparatuses

The present invention provides both differential and integral non-linearity measurement capabilities with a minimum of additional hardware and a test time reduction of several orders of magnitude. The test circuit for N delay lines includes a ring oscillator that has a select signal and an output. A counter is connected in parallel with the ring oscillator. An arithmetic logic unit receives a &ldquo;COMPARE&rdquo; value from a register and the counter output. An upper and a lower bound register store acceptable tolerances for non-linearity. Each comparator, upper and lower bound, receives the tolerance stored in the corresponding register and the output of the arithmetic logic unit. An AND gate receives the outputs of the upper and lower bound comparators and generates a signal indicative of the state of the oscillator.

Method for delay line linearity testing

A pulse width modulator includes a clock operative to count successive discrete time intervals having a period equal to a desired full pulse width, and configured to generate a clock signal. The pulse width modulator also includes an adjustable delay line comprising a plurality of delay line elements, each delay line element operative to generate a clock signal at a specific location, which when combined with a transitional instruction, will produce a modulated output that has a plurality of transitions within the clock period. The pulse width modulator further includes processing circuitry configured to receive the clock signal and a pulse code input and operative to select one of the delay line elements to generate a clock signal at a specific location to produce a single modulated output that transitions at a desired modulated frequency. A method is also provided.

Pulse width modulator using delay-line technology with automatic calibration of delays to desired operating frequency

An electrophotographic imaging device uses a transition placement device to position transitions in a stream of video data. A rasterizer included in the electrophotographic imaging device generates pixel data bytes based upon data received from a computer defining an image. A converter generates codes specifying positions of transitions within a pixel time period corresponding to a pixel data byte. The transition placement device includes a phase measuring device to measure a timing offset between an active edge of a beam detect signal and a rising edge of a reference clock. A transition adjustment device adjusts the positions of the transitions specified by the codes relative to the rising edge of the reference clock using the timing offset. Transition generation logic generates the transitions for the stream of video data using the adjusted transition positions received from the transition adjustment device. If the adjusted positions of the transitions shift the occurrence of the transitions to the next cycle of the reference clock, the transition adjustment device determines the position of the transitions relative to the rising edge of the reference clock into which the transitions were shifted. Registers included in a next cycle transition storage device delay the transitions shifted to the next cycle by one reference clock cycle before application to the transition generation logic.

Method and device for time shifting transitions in an imaging device

An embodiment of an edge placement device is supplied with transition data to generate transitions during a pixel time period corresponding to the transition data. The transition data is supplied by pulse code logic that converts pixel data to the transition data. The embodiment of an edge placement device includes first edge placement logic coupled to taps from a first clock delay chain and second edge placement logic coupled to taps of a second clock phase delay chain. Also included is a phase splitter that generate a first and a second clock phase coupled, respectively, to the first and the second clock delay chain from a clock corresponding to a pixel time period. The first and the second clock phase have rising edges on alternate cycles of the clock. The first and the second edge placement logic each include a plurality of D flip flops. The clock inputs of each of the flip flops in the first and the second edge placement logic are coupled, respectively, to one tap from first or the second clock delay chain. The D inputs of the flip flops of the first and the second placement edge placement logic are coupled, respectively, to a first and a second data phase provided by the pulse code logic. By setting the values of the first and the second data phases, supplied on alternate cycles of the clock, video data is generated having transitions during the pixel time period corresponding to the pixel data.

Edge placement device

Text and line art image data is distinguished from halftone image data for selectively enhanced rendering thereof. Specifically, a method of rendering a raster pixel image from a stored bitmap includes (i) determining whether an orphan pixel is detected within a bounded sampling window of the bitmap, and, (ii) processing at least one selected pixel of the bitmap within the sampling window relative to the determining of whether an orphan pixel is detected. In general, an orphan pixel is defined as an isolated white or black pixel in a halftone image. In one embodiment, an orphan pixel is recognized as having a predefined pixel value and as having no other pixels with that value adjacent thereto within the sampling window. In the event an orphan pixel is detected within the window, then the bitmap within the window is determined to be halftone image data and the selected pixel is processed accordingly. In the event an orphan pixel does not exist within the window, then the bitmap within the window is recognized as text or line art image data and processed respectively. In addition, a method of forming a dither matrix for a halftone image includes generating a pixel pattern such that an orphan pixel exists within the pattern of the dither matrix. The orphan pixel is designed into the halftone image. This measure increases the probability that orphan pixels will exist and be detected in the resultant raster image array. Thus, during subsequent rendering of the raster pixel image, selective application of resolution enhancement techniques may occur based on whether or not an orphan pixel is detected in the sampling window.

Encoded orphan pixels for discriminating halftone data from text and

An apparatus derives data to enable a fill action during operation of a print device along a scan line. The apparatus includes a processor which determines, for each of a sequence of contours of a glyph, point of intersection values between a scan line and the contours. The sequential point of intersection values indicate OFF-to-ON and ON-to-OFF transitions required of the print device. Sequential OFF-to-ON and ON-to-OFF transitions comprise a transition pair. The apparatus includes a memory comprising 2N storage positions for storage of N transition pairs. Comparator circuitry is coupled in parallel to the 2N storage positions. A controller operates the comparator circuitry to determine an order of all OFF-to-ON point of intersection values and an order of all ON-to-OFF point of intersection values in the 2N storage positions. Switch circuitry is responsive to the determined order of OFF-to-ON point of intersection values to re-order the OFF-to-ON point of intersection values in the 2N storage positions and is further responsive to the determined order of the ON-to-OFF point of intersection values to re-order the ON-to-OFF point intersection values in the 2N storage positions. Overlap regions are determined and transition pairs to be arranged so that overlap regions are ignored.

Growing community of inventors

Boise, ID, United States of America

Eugene A Roylance