Massachusetts Institute of Technology

Amberwave Systems Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Nanyang Technological University

National University of Singapore

4power, LLC

The Charles Stark Draper Laboratory, Inc.

The Water Initative, LLC

Amberwave Systems Corproation

New Silicon Corporation Pte Ltd

Eugene A Fitzgerald

Matthew T Currie

Anthony J Lochtefeld

Richard Hammond

Thomas A Langdo

Dimitri A Antoniadis

Minjoo Larry Lee

Kwang Hong Lee

Christopher W Leitz

Chuan Seng Tan

Eng Kian Kenneth Lee

Soo Jin Chua

Li Hong Zhang

Richard Charles Westhoff

Christopher J Vineis

Mayank T Bulsara

Judy L Hoyt

Zhiyuan Cheng

Zhi-Yuan Cheng

Jeffrey T Borenstein

Shuyu Bao

Arthur J Pitera

Kenneth C Wu

Nicole Gerrish

Joseph Sylvester Chang

Glyn Braithwaite

Wei Shu

Siau Ben Chiah

Kenneth Eng Kian Lee

Yong Qu

John J Hennessy

Andrew C Malonis

Steven A Ringel

Saurabh Gupta

David Michael Isaacson

Ya-Hong Xie

Jurgen Michel

Chirn Chye Boon

Bing Wang

Cheng Yeow Ng

Carl V Thompson

Pilsoon Choi

Yiding Lin

Richard Renjilian

Michael J Mori

Yu Bai

Viet Cuong Nguyen

Gianni Taraschi

Carl Dohrman

Lisa McGill

Yew Heng Tan

Arthuer J Pitera

Gang Yih Chong

Andrew Y Kim

Gianna Taraschi

Srikanth B Samavedam

Prithu Sharma

Timothy Milakovich

Fayyaz Moiz Singaporewala

Keith Cheng Yeow Ng

A method of fabricating a semiconductor device () is described. According to a described embodiment, the method comprises: (i) forming a III-V semiconductor material layer () comprising a substrate layer () and a device layer () attached to the substrate layer (); and (ii) forming an electrically conductive interlayer () to the device layer () prior to bonding the electrically conductive interlayer () to a partially processed CMOS device layer () having at least one transistor ().

Method for fabricating a semiconductor device including integrating III-V device and CMOS device, and the semiconductor device thereof

Disclosed is a method of reducing surface unevenness of a semiconductor wafer (). In a preferred embodiment, the method comprises: removing a portion of a deposited layer and a protective layer thereon using a first slurry to provide an intermediate surface (). In the described embodiment, the deposited layer includes an epitaxial layer () and the protective layer includes a first dielectric layer (). The first slurry includes particles with a hardness level the same as or exceeding that of the epitaxial layer (). A slurry for use in wafer fabrication for reducing surface unevenness of a semiconductor wafer is also disclosed.

Method of reducing semiconductor substrate surface unevenness

An apparatus and method for wireless communication, and a method of fabricating the apparatus. The apparatus comprises two or more transceiver array groups, each transceiver array group comprising one or more radio frequency, RF, circuits, and one or more RF front end, RF FE, circuits; wherein the transceiver array groups are configured to operate at different frequencies; wherein the transceiver array groups are configured to be connected to one corresponding digital baseband processor; and wherein the transceiver array groups comprise at least one first transceiver array group configured to operate at cm wavelength or larger. Preferably, the transceiver array groups comprise at least one second transceiver array group configured to operate at mm wavelength.

Apparatus and method for wireless communication

Disclosed is a subpixel circuitcomprising: a first switching deviceresponsive to a digital periodic signal Vto provide a digital control signal Vrelating to a digital data signal V, the digital periodic signal Vdefining 2+1 time slots within each frame cycle, where N is a predetermined integer. The digital data signal Vhas a predetermined value at a predetermined one of the 2+1 time slots; and the subpixel circuitfurther comprises a second switching deviceresponsive to the control signal Vc to drive an associated light emitting element

Subpixel circuitry for driving an associated light element, and method, display system and electronic device relating to same

A method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display is provided. The method comprising providing a first wafer comprising first layers disposed over a first substrate, said first layers comprising non-silicon based semiconductor material for forming p-n junction LEDs (light emitting devices); providing a second partially processed wafer comprising silicon-based CMOS (Complementary Metal Oxide Semiconductor) devices formed in second layers disposed over a second substrate, said CMOS devices for controlling the LEDs; and bonding the first and second wafers to form a composite wafer via a double-bonding transfer process.

Method of forming a multilayer structure for a pixelated display and a multilayer structure for a pixelated display

A method of fabricating a device on a carrier substrate, and a device on a carrier substrate. The method comprises providing a first substrate; forming one or more device layers on the first substrate; bonding a second substrate to the device layers on a side thereof opposite to the first substrate; and removing the first substrate.

Fabrication of a device on a carrier substrate

A method of encapsulating a substrate is disclosed, in which the substrate has at least the following layers: a CMOS device layer, a layer of first semiconductor material different to silicon, and a layer of second semiconductor material, the layer of first semiconductor material arranged intermediate the CMOS device layer and the layer of second semiconductor material. The method comprises: (i) circumferentially removing a portion of the substrate at the edges; and (ii) depositing a dielectric material on the substrate to replace the portion removed at step (i) for encapsulating at least the CMOS device layer and the layer of first semiconductor material. A related substrate is also disclosed.

Method of encapsulating a substrate

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Methods of forming strained-semiconductor-on-insulator device structures

A method of manufacturing a substrate with reduced threading dislocation density is disclosed, which comprises: (i) at a first temperature, forming a first layer of wafer material on a semiconductor substrate, the first layer arranged to be doped with a first concentration of at least one dopant that is different to the wafer material; and (ii) at a second temperature higher than the first temperature, forming a second layer of the wafer material on the first layer to obtain the substrate, the second layer arranged to be doped with a progressively decreasing concentration of the dopant during formation, the doping configured to be decreased from the first concentration to a second concentration. The wafer material and dopant are different to silicon. A related substrate is also disclosed.

Method of manufacturing a substrate with reduced threading dislocation density

A method of manufacturing a germanium-on-insulator substrate is disclosed, comprising: (i) doping a first portion of a germanium layer with a first dopant to form a first electrode, the germanium layer arranged with a first semiconductor substrate; (ii) forming at least one layer of dielectric material adjacent to the first electrode to obtain a combined substrate; (iii) bonding a second semiconductor substrate to the layer of dielectric material and removing the first semiconductor substrate from the combined substrate to expose a second portion of the germanium layer with misfit dislocations; (iv) removing the second portion of the germanium layer to enable removal of the misfit dislocations and to expose a third portion of the germanium layer; and (v) doping the third portion of the germanium layer with a second dopant to form a second electrode. The electrodes are separated from each other by the germanium layer, and the first dopant is different to the second dopant.

Method of manufacturing a germanium-on-insulator substrate

Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or 'FETs') that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.

Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same

A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing () a first semiconductor substrate, and a second semiconductor substrate formed with a germanium layer; bonding () the first semiconductor substrate to the second semiconductor substrate using at least one dielectric material to form a combined substrate, the germanium layer being arranged intermediate the first and second semiconductor substrates; removing () the second semiconductor substrate from the combined substrate to expose at least a portion of the germanium layer with misfit dislocations; and annealing () the combined substrate to enable removal of the misfit dislocations from the portion of the germanium layer.

A method of manufacturing a substrate is disclosed. The method comprises: providing a first semiconductor substrate, which includes an at least partially processed CMOS device layer and a layer of first wafer material; bonding a handle substrate to the partially processed CMOS device layer and removing the layer of first wafer material; providing a second semiconductor substrate having a layer of second wafer material which is different to silicon; bonding the first and second semiconductor substrates to form a combined substrate by bonding the layer of second wafer material to the partially processed CMOS device layer; and removing the handle substrate from the combined substrate to expose at least a portion of the partially processed CMOS device layer.

Method of manufacturing a substrate

The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. A structure includes a relaxed substrate including a bulk material, a strained layer directly on the relaxed substrate, where a strain of the strained layer is not induced by the relaxed substrate, and a transistor formed on the strained layer.

Methods for forming semiconductor device structures

Growing community of inventors

Windham, NH, United States of America

Eugene A Fitzgerald