Mitsubishi Denki Kabushiki Kaisha

Etsuko Okushi

Mitsuhiro Yasuda

J Barry Shackleford

Takashi Iwamoto

A fitness function circuit for computing a fitness value for a trial solution to a set covering problem accelerates the execution speed of a genetic algorithm provided with a matrix circuit for outputting a column signal covered by a row signal corresponding to a bit in a chromosome, a column signal counter for counting column signals, a subtractor for calculating a difference between a counted number of column signals and a number of all elements and outputting the difference as a number of uncovered elements, a carry-save-adder for outputting a number of valid row signals as a chromosome cost, an aggregate cost register for holding the number of uncovered elements as a more significant portion of a total cost and the chromosome cost as a less significant portion of the total cost and outputting the total cost, an inverter for inverting a value of the total cost and outputting an inverted value as a fitness value.

Fitness function circuit

A multi-purpose non-problem-specific hardware-based framework for the execution of a genetic algorithm (GA) accelerates the execution speed of a GA through the implementation of hardware-based non-problem-specific functions of population memory, first and second chromosome registers, crossover module, mutation operator, and survival comparator. The non-problem-specific aspect of the hardware-based framework turns problem-specific without changing the contents of the framework once a problem-specific fitness function circuit is included for evaluating chromosomal data representing a potential problem solution. The hardware-based framework is thus applicable to a variety of problem-specific aspects of the problem-specific fitness function circuit.

Genetic algorithm machine and its production method, and method for

The present invention provides a processor synthesis system and a processor synthesis method which enable a designer to synthesize a CPU that does not depend on a specific process technology and has the bit width customized to the requirements of the specific application. The processor synthesis method according to the present invention comprises steps of generating and outputting processor definition information to define a CPU based on primary parameters entered by the designer; generating a compiler and an assembler for generating an instruction code for the CPU defined by the processor definition information; and executing simulation using the instruction code output by the generated compiler and the assembler so as to facilitate optimization of the designed CPU and reduce development costs.

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Tokyo, Japan

Etsuko Okushi