Semiconductor Energy Laboratory Co., Ltd.

Sharp Kabushiki Kaisha, Co., Ltd.

Etsuko Asano

Kiyoshi Kato

Masahiko Hayakawa

Masayuki Sakakura

Yutaka Shionoiri

Tetsuji Yamaguchi

Osamu Nakamura

Tatsuya Arao

Takuya Tsurume

Hidehito Kitakado

Takuya Matsuo

Saishi Fujikawa

Takashi Yokoshima

Tatsuya Honda

Konami Izumi

Tomoya Futamura

Naomi Yazaki

Tomoko Nishikawa

Yoshiko Ikeda

To provide a semiconductor device capable of being easily subjected to a physical test without deteriorating characteristics. According to a measuring method of a semiconductor device in which an element layer provided with a test element including a terminal portion is sealed with first and second films having flexibility, the first film formed over the terminal portion is removed to form a contact hole reaching the terminal portion; the contact hole is filled with a resin containing a conductive material; heating is carried out after arranging a wiring substrate having flexibility over the resin with which filling has been performed so that the terminal portion and the wiring substrate having flexibility are electrically connected via the resin containing a conductive material; and a measurement is performed.

Semiconductor device, manufacturing method thereof, and measuring method thereof

An easy-to-use and inexpensive memory device is provided while maintaining product specifications and productivity even when a memory is formed on the same substrate as other functional circuits. The memory device of the invention includes a memory cell formed on an insulating surface. The memory cell includes a semiconductor film having two impurity regions, a gate electrode, and two wirings connected to the respective impurity regions. The two wirings are insulated from each other by applying a voltage between the gate electrode and at least one of the two wirings to alter the state of the semiconductor film.

Memory device and manufacturing method of the same

A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof. The manufacturing method of the semiconductor device comprises the steps of: forming first and second semiconductor layers over a substrate, forming a first insulating film over the first and second semiconductor layers, forming first and second conductive films thereover, forming a first gate electrode having a stacked layer of the first and second conductive films, in which a portion of the first conductive film is exposed from the second conductive film, over the first semiconductor layer with the first insulating film interposed therebetween, forming a second insulating film over the first insulating film, forming third and fourth conductive films thereover, and forming a second gate electrode having a stacked layer of the third and fourth conductive films, in which a portion of the third conductive film is exposed from the fourth conductive film, over the second semiconductor layer with the first and second insulating films interposed therebetween.

Semiconductor device and manufacturing method thereof

The present invention provides a method for evaluating an intended element or a parameter. In addition, the invention provides an evaluation method for obtaining a more precise result rapidly. According to the invention, a plurality of evaluation circuits are formed over the same substrate, and while simultaneously operating the plurality of evaluation circuits, an output of one evaluation circuit selected by a selection circuit that is formed over the substrate is arbitrarily evaluated.

Method for evaluating semiconductor device

The reliability of a GOLD structure TFT depends on an impurity concentration in its gate-overlapped region. Thus, it is an object of the present invention to obtain a resistance distribution corresponding to a tapered shape of a gate electrode in a gate-overlapped region. According to the present invention, plural TEGs are manufactured as Lov resistance monitors in which mask alignment is misaligned with several &#x3bc;m interval to perform a resistance measurement on each of the TEGs. Consequently, a resistance distribution corresponding to a tapered shape can be obtained in a channel forming region, a gate-overlapped region and a source/drain region.

Evaluation method using a TEG, a method of manufacturing a semiconductor device having the TEG, an element substrate and a panel having the TEG, a program for controlling dosage and a computer-readable recording medium recording the program

The present invention provides a method for manufacturing a semiconductor device having high characteristic and reliability. The etching damage during dry etching after forming an electrode or a wiring over an insulating film is prevented. The damage is suppressed by forming a conductive layer so that charged particles due to plasma during dry etching are not generated in a semiconductor layer. Accordingly, it is an object of the invention to provide a method not for generating the deterioration of the transistor characteristic especially in a thin film transistor having a minute structure.

Method for manufacturing semiconductor device

The invention performs an AC stress test assuming the CMOS operation and an AC stress test using a ring oscillator (R.O.) between a DC stress test method using single semiconductor elements and an aging test method. The deterioration of a semiconductor apparatus can be estimated highly precisely by separately performing the AC stress test assuming the CMOS operation on OFF-stress and ON-stress.

Method and apparatus for examining semiconductor apparatus and method for designing semiconductor apparatus

Evaluation method using a TEG, a method of manufacturing a semiconductor device having a TEG, an element substrate and a panel having the TEG, a program for controlling dosage and a computer-readable recording medium recoding the program

It is an object of the present invention to provide a method for evaluating a semiconductor device including a semiconductor, an insulator, and a conductor. The present invention has a first step of applying a voltage to a conductor to measure a current value, a second step of dividing the current value by an area of a region in which a semiconductor is overlapped with the conductor to calculate a current density Jg, and a third step of calculating a depletion layer edge leakage current and an in-plane leakage current by using coefficients of a formula Jg=2A/r+B (A and B are respectively constants) that has a reciprocal of the radius r and the current density Jg. Alternatively, the present invention has the first step, the second step, and another third step of using coefficients of a formula Jg=A/W+B/L+C (A, B, and C are respectively constants) that has reciprocals of a channel width W and a channel length L of the semiconductor and the current density Jg to calculate a depletion layer edge leakage current, an in-plane leakage current, and a silicon edge leakage current.

Growing community of inventors

Atsugi, Japan

Etsuko Asano