Mentor Graphics Corporation

Etienne Racine

Martin Keim

Ronald Press

Jean-Francois Cote

Wu-Tung Cheng

Yu Hu

Yu Jane Huang

Ruifeng Guo

Liyang Lai

Jing Ye

Aspects of the invention relate to test access architecture for stacked memory and logic dies. A test access interface for a logic die that is stacked under a memory die is disclosed. The disclosed test access interface can control testing logic core, interconnections with the memory die and with another logic die. The controlling of testing interconnections with the memory die is through a memory boundary scan register controller in the test access interface.

Test access architecture for stacked memory and logic dies

Aspects of the invention relate to test access architecture for stacked dies. The disclosed test access interface for a die can function as a stand-alone test access interface, allowing both pre-bond testing and post-bond testing of the die. In a stack of dies, the test access interface of a die may be enabled/disabled by the test access interface of an adjacent die.

Test access architecture for multi-die circuits

Test access architecture for stacked dies

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Blainville, Canada

Etienne Racine