Synopsys, Inc.

Etienne Lepercq

Sankaranarayanan Srinivasan

Vinod Kumar Nakkala

Avinash Anantharamu

Senthilkumar Thoravi Rajavel

Pierre Clement

Saibal Ghosh

Sashikala Oblisetty

Alexander Rabinovitch

Jiahua Zhu

Jiong Cao

Marc-Andre Daigneault

A method includes storing a base model generated using base data and receiving training data generated by compiling circuit designs. The method also includes generating, using the training data, a tuned model and generating, using the training data and the base data, a hybrid model. The method further includes receiving a selected cost function and biasing the base model, the tuned model, and the hybrid model using the selected cost function.

Machine-learning enhanced compiler

A method includes generating a netlist for a circuit design and predicting, by applying a first machine learning model to the netlist, a first compile time for the circuit design. The method also includes predicting, by applying a second machine learning model to the netlist, a first place and route strategy based on the first compile time. The method further includes adjusting a logic of the circuit design in accordance with the first place and route strategy.

A computer-implemented method generates a plurality of clusters based on components included in a design under test (DUT); classifies a subset of clusters of the plurality of clusters as tangled clusters; modifies at least two tangled clusters of the subset of clusters based on overlap between the at least two tangled clusters; determines, for each tangled cluster in the subset of clusters, a gate count based on the interconnectivity of the tangled cluster; and partitions the DUT among a plurality of field-programmable gate arrays (FPGAs) based on the gate count determined for each tangled cluster from the subset of clusters.

Peak wirelength aware compiler for FPGA and FPGA-based emulation

A computer-implemented method for configuring a hardware verification system includes receiving, in the computer, a first data representative of a first design. The method further includes performing a first mapping of the first data to generate a second data in accordance with a first cost function and one or more first delays each associated with a different one of a first multitude of paths. One of the first multitude of paths includes a critical path characterized by a second delay. The method further includes performing a second mapping of the second data to generate a third data in accordance with a second cost function and a multitude of third delays each associated with a different one of a second multitude of paths and the second delay. The method further includes compiling the third data for configuring the hardware verification system.

Partitioning and routing multi-SLR FPGA for emulation and prototyping

A method of emulating a circuit design using an emulator is presented. The method includes allocating one or more spare routing resources to one or more field programmable gate array (FPGA) routing sockets when compiling a plurality of FPGAs disposed in the emulator in preparation for emulating the circuit design, and using the one or more spare routing resources to provide one or more routings among the FPGAs in response to one or more changes made to the circuit design.

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Shrewsbury, MA, United States of America

Etienne Lepercq