International Business Machines Corporation

The Boeing Company

Globalfoundries Inc.

Ethan Harrison Cannon

Alvin Wayne Strong

John M Aitken

Toshiharu Furukawa

Charles W Koburger, Iii

Manuel F Cabanas-Holmen

Jack Allan Mandelman

David V Horak

Philip Joseph Oldiges

Salim A Rabaa

William R Tonti

Timothy Dooling Sullivan

Michael J Hauser

Kerry Bernstein

John Edward Barth, Jr

K Paul Muller

Aj KleinOsowski

Steven J Holmes

Tak H Ning

Michael S Gordon

Mark Charles Hakey

Kenneth Parker Rodbell

Wagdi William Abadeer

Dieter F Wendel

James Douglas Warnock

Leon Jacob Sigal

John Gerard Gaudiello

Francis Roger White

Dennis T Cox

Fen Chen

Alan J Drake

Fadi Hikmat Gebara

Mark Joseph Clemen, Jr

Shunhua Thomas Chang

David F Heidel

John Patrick Keane

Theodore Harold Zabel

Carl Emil Bohnenkamp

Alicia Wang

Christopher D LeBlanc

Ethan W Cascio

Mark Yao

Josh Mackler

A solid-state device having a substrate that receives an ionizing radiation, logic circuits, integrity circuits, and a collection circuit. The logic circuits are operational to perform logic functions. The logic circuits are located in an area on the substrate, and are individually susceptible to a possible corruption by the ionizing radiation. Each integrity cell is initialized to a predetermined state. The integrity cells are located in the area on the substrate, arranged in a pattern neighboring the logic circuits, and individually susceptible to disrupting the predetermined state in response to the ionizing radiation. The collection circuit is located on the substrate. The collection circuit is operational to read the plurality of integrity cells, and assert a report signal that identifies the possible corruption in a subset of the logic circuits due to the ionizing radiation in response to reading an incorrect state in a neighboring one of the integrity cells.

Radiation induced error detection in solid-state devices

A flip-flop circuit comprises a pass gate, a feedback inverter, and an interleaved filter. The pass gate comprises a clock input and an inverting clock input. The feedback inverter includes a feedback input coupled to both the clock input and the inverting clock input of the pass gate. The interleaved filter comprises a delay circuit including a delay output, a C-gate element, and a blocking inverter. The C-gate element includes a C-gate input and a C-gate output. The C-gate input is coupled to the delay output of the delay circuit and the pass gate, and the C-gate output is coupled to the feedback input of the feedback inverter. The blocking inverter includes a blocking input and a blocking output. The blocking input is coupled to the delay output of the delay circuit, and the blocking output is coupled to the feedback input of the feedback inverter.

Radiation hardened flip-flop circuit for mitigating single event transients

A test structure for measuring static noise margin (SNM) for one or more static random access memory (SRAM) cells can include a first transistor gate (TG) and a second TG electrically coupled to each SRAM cell. In an implementation, an interconnect between an output of a first inverter and an input of a second inverter of the SRAM cell can be electrically disconnected using a cut off. During operation of the SRAM cell, internal storage nodes within the SRAM cell can be electrically coupled through the first TG and the second TG to, for example, external pins and to a test fixture. Electrical parameters such as voltage can be measured at the internal storage nodes through the external pins and used to calculate SNM of the SRAM cell.

Direct measurement test structures for measuring static random access memory static noise margin

Systems and methods to ensure correct operation of a semiconductor chip in the presence of ionizing radiation is disclosed. The system includes a semiconductor chip, a first radiation detection array incorporated in the semiconductor chip, and at least one additional radiation detection array incorporated in the semiconductor chip. a processor determines a region of the semiconductor chip affected by an incident radiation particle by analyzing a trajectory of the radiation particle determined from locations of sensors hit by the radiation particle in the first radiation detection array and the at least one additional radiation detection array. The processor determines whether corrective action is needed based on the region of the semiconductor chip affected by the incident radiation particle.

Structure and method to ensure correct operation of an integrated circuit in the presence of ionizing radiation

Each one of a pair of CMOS transistors is formed in its own island and a gate terminal for each transistor is formed by a single, in-line conductor connecting both gate terminals together. This type of 'in-line' connection achieves nearly a five-time improvement in the reduction of the ability of ionizing radiation particles to strike both transistors at the same time as compared to prior art 'side-by-side' transistor stacking through use of a relatively smaller solid angle spanning the two transistors. This results in &#x201c;hardening&#x201d; of the transistors and improving their resistance to single event upsets and, thus, improving the soft error rate (SER) of the transistors.

In-line stacking of transistors for soft error rate hardening

A flip flop circuit has a first stage and a second stage. The first stage and the second stage each have interleaved filters.

Filtered radiation hardened flip flop with reduced power consumption

A circuit and methods for mitigating radiation-induced Single Event Effects (SEE) in Silicon-on-Insulator (SOI) Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuits are presented. A primary logic output is generated from a primary logic gate in response to an input. A redundant logic output is generated from a redundant logic gate that duplicates the primary logic output in response to the input if an SEE is not present. An interleaved C-gate output is generated from an interleaved C-gate that emulates an inverter output when the primary logic output and the redundant logic output match, and does not changes its output when the primary logic output and the redundant logic output do not match during the SEE.

Single event transient and upset mitigation for silicon-on-insulator CMOS technology

An interleaved filter circuit has a delay element configured to receive an input signal. An interleaved output buffer has a first input which receives the input signal and a second input which receives the output of the delay element. An output of the interleaved output buffer is driven when the first input and the second input are at a same logic level.

Interleaved transient filter

An array of radiation sensors or detectors is integrated within a three-dimensional semiconductor IC. The sensor array is located relatively close to the device layer of a circuit (e.g., a microprocessor) to be protected from the adverse effects of the ionizing radiation particles. As such, the location where the radiation particles intersect the device layer can be calculated with coarse precision (e.g., to within 10 s of microns).

Array of alpha particle sensors

A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

Apparatus and method for hardening latches in SOI CMOS devices

A digital logic storage structure includes cross coupled first and second complementary metal oxide semiconductor (CMOS) inverters formed on a semiconductor substrate, the CMOS inverters including a first storage node and a second storage node that is the logical complement of the first storage node; both of the first and second storage nodes each selectively coupled to a deep trench capacitor through a switching transistor, with the switching transistors controlled by a common capacitance switch line coupled to gate conductors thereof; wherein, in a first mode of operation, the switching transistors are rendered nonconductive so as to isolate the deep trench capacitors from the inverter storage nodes and, in a second mode of operation, the switching transistors are rendered conductive so as to couple the deep trench capacitors to their respective storage nodes, thereby providing increased resistance of the storage nodes to single event upsets (SEUs).

Structure and method for improving storage latch susceptibility to single event upsets

The different advantageous embodiments provide an integrated circuit comprising a number of latches and a number of filters. Each latch in the number of latches has a plurality of inputs and a plurality of storage nodes. The plurality of storage nodes includes a number of pairs of circuit nodes that form a number of upsettable circuit node pairs. Each input of the plurality of inputs is connected to a corresponding storage node in the plurality of storage nodes. Each filter in the number of filters has an input and a plurality of outputs. Each of the plurality of outputs is connected to a corresponding input of the plurality of inputs of a latch in the number of latches. Each filter in the number of filters is located between two circuit nodes forming an upsettable circuit node pair of the latch in the number of latches to increase critical node spacing.

Method and apparatus for reducing radiation and cross-talk induced data errors

An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200&#xb0; C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.

On-chip heater and methods for fabrication thereof and use thereof

A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.

Deep trench capacitor for SOI CMOS devices for soft error immunity

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Essex Junction, VT, United States of America

Ethan Harrison Cannon