Apple Inc.

Texas Instruments Corporation

Etai Zaltsman

Avraham Poza Meir

Ori Moshe Stern

Oren Golov

Sasha Paley

Naftali Sommer

Eyal Gurgi

Yoav Kasorla

Shai Ojalvo

Yael Shur

Moshe Neerman

Meir Dalal

Ofir Shalvi

Julian Vlaiko

Zvi Reznic

Barak Baum

Liran Fishel

Assaf Shappir

Liran Brecher

Christopher John Sarcone

Amos Klimker

Manoj K Radhakrishnan

Danny Gal

Guy Ben-Yehuda

Roman Gindin

Nir Nissan

Yoni Labenski

Moti Altahan

Yoram Harel

Embodiments of the present disclosure relate to an accelerator circuit with a dynamic immediate values table (IVT). The accelerator circuit includes an instruction memory, a data memory, and a vector circuit with the IVT storing multiple immediate values at multiple entries. The vector circuit reads a subset of instructions from the instruction memory, each instruction including at least one corresponding pointer to at least one corresponding entry in the IVT. The vector circuit further receives a subset of input data from the data memory corresponding to the subset of instructions. The vector circuit performs a respective operation in accordance with each instruction from the subset of instructions using a corresponding data vector of the received subset of input data identified in each instruction and at least one corresponding immediate value from the IVT pointed by the at least one corresponding pointer to generate corresponding output data.

Accelerator circuit for mathematical operations with immediate values table

Disclosed herein is a technique for maintaining a responsive user interface for a user while preserving battery life of a user device by dynamically determining the interrupt rate/interrupt time at the user device. Based on priority tier information associated with the I/O requests along with the directionality and size of the I/O requests, a determination can be made regarding how the interrupt rate/interrupt time can be adjusted to achieve acceptable user interface (UI) responsiveness and maximum power savings.

Power saving feature for storage subsystems

A method in a storage device includes receiving from a host storage commands for execution in a non-volatile memory of the storage device. At least a subset of the storage commands are to be executed in accordance with an order-of-arrival in which the storage commands in the subset are received. The received storage commands are executed in the non-volatile memory in accordance with internal scheduling criteria of the storage device, which permit deviations from the order-of-arrival, but such that execution of the storage commands in the subset reflects the order-of-arrival to the host.

Efficient enforcement of command execution order in solid state drives

A controller includes an interface and a processor. The interface is configured to communicate with a memory including multiple memory cells organized in at least two sections each including multiple sets of word lines (WLs), wherein in a first failure mode multiple WLs fail in a single section, and in a second failure mode a WL fails in multiple sections. The processor is configured to assign multiple cell-groups of the memory cells to a parity-group, such that (i) no two cell-groups in the parity-group belong to a same WL, and (ii) no two cell-groups in the parity-group belong to adjacent WLs in a same section, and, upon detecting a failure to access a cell-group in the parity-group, due to either the first or second failure modes but not both failure modes occurring simultaneously, to recover the data stored in the cell-group using one or more remaining cell-groups in the parity-group.

Data recovery in memory having multiple failure modes

A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.

Parallel scheduling of write commands to multiple memory devices

A method for data storage includes, for a memory including groups of memory cells, defining a normal mode and a protected mode, wherein in the protected mode a respective analog value of each memory cell remains at all times unambiguously indicative of a respective data value stored in that memory cell. Data is initially stored in the memory using the normal mode. In response to an event, the protected mode is reverted to for at least one of the groups of the memory cells.

Protection and recovery from sudden power failure in non-volatile memory devices

An apparatus includes a non-volatile memory and a processor. The processor is configured to receive, from a host, commands for storage of data in the non-volatile memory, to further receive from the host, for storage in the non-volatile memory, File System (FS) information that specifies organization of the data in a FS of the host, to receive from the host a directive that grants the processor permission and capability to access and modify the FS information, and to access the FS information, using the directive, so as to manage the storage of the data in the non-volatile memory.

Memory system with shared file system

A method includes, in a memory controller that controls a memory, evaluating an available memory space remaining in the memory to write data. A redundant storage configuration is selected in the memory controller depending on the available memory space. Redundancy information is calculated over the data using the selected redundant storage configuration. The data and the redundancy information are written to the available memory space in the memory.

Selection of redundant storage configuration based on available memory space

A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.

Mitigating reliability degradation of analog memory cells during long static and erased state retention

A method includes, in a non-volatile memory that includes multiple memory blocks, defining a redundancy zone that includes at least an old parity block, a new parity block and multiple active blocks of which one block is defined as an open block. Data is stored in the redundancy zone and the stored data is protected, such that new input data is stored in the open block, redundancy information for the active blocks including the open block is stored in the new parity block, and the redundancy information for the active blocks excluding the open block is stored in the old parity block. Upon filling the open block and the new parity block, an alternative block is assigned to serve as the open block and the new parity block is assigned to serve as the old parity block.

Redundancy schemes for non-volatile memory using parity zones having new and old parity blocks

A novel apparatus and method of packet re-sequencing applicable to systems wherein packets are assigned sequence numbers and transmitted over multiple channels with the requirement they be re-ordered at the receiving side. The mechanism is particularly suitable for use in cable systems adapted to implement the DOCSIS 3.0 specification which permits the bonding of a plurality of downstream channels into a single virtual high data rate pipe. In operation, received packets are stored in a memory whereby a pointer to the memory storage location is written into a context table diagram in accordance with the sequence number extracted from the packet. Packets are released in sequence order regardless of the order in which they were received.

Cable modem downstream channel bonding re-sequencing mechanism

A method and device for combating logarithmic quantization and Robbed Bit Signaling (RBS) impairments that..are typical to PCM telephone lines is descried. An apparatus is described which includes a front-end unit which receives samples of the digital PCM line, an impairment identifier unit which identifies samples that have a high likelihood to have, large impairments due to the PCM line, an impairment estimator unit which estimates the value of impairment caused by the digital line, a samples reconstructor unit which fixes received samples by subtracting from them the value of the estimated impairment and an output unit transfers the reconstructed samples to a receiver. The method allows improving signal quality at the output of the PCM line, and thus improving data rates and robustness of digital communication receivers, and particularly of V.34 receivers, or V.90 transceivers that are digitally linked to the PCM, line.

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Ramat-Hasaron, Israel

Etai Zaltsman