Freescale Semiconductor,inc.

Western Digital Technologies, Inc.

Eswaran Subramaniam

Sathyanarayanan Subramanian

Jatin Gaur

Vikas Chouhan

Puneet Aggarwal

Systems and methods for offloading computational operations. In some implementations a method includes determining whether a data storage device coupled to a computing device is capable of performing a set of computational operations. The data storage device may be hot swappable. The method also includes offloading the set of computational operations to the data storage device in response to determining that the data storage device is capable of performing the set of computational operations. The method further includes performing the set of computational operations on the computing device in response to determining the data storage device is not capable of performing the set of computational operations.

Transferring computational operations to controllers of data storage devices

A cache lock validation apparatus for a cache having sets of cache lines and coupled to a cache controller. The apparatus includes a memory coupled to a processor. The memory includes test case data related to an architecture of the cache. The processor selects a first set of the sets of cache lines and generates a corresponding first group of addresses and an overflow status address. The processor instructs the cache controller to sequentially lock the first group of addresses and the overflow status address. The processor checks a status of an overflow bit in a status register of the cache controller upon locking the overflow status address, and generates a FAIL status signal when the overflow bit is reset.

System and method for validation of cache memory locking

A method of testing the coherency of data storage in a memory shared by multiple processor cores through core interconnects in a device under test (DUT) includes running test patterns including data transactions between the processor cores and the shared memory, and comparing the results of the data transactions with expected results. The test patterns include false sharing operations and irritator operations causing memory thrashing.

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Bengaluru, India

Eswaran Subramaniam