International Business Machines Corporation

University of South Carolina

Essam Mina

Guoan Wang

Wayne Harvey Woods, Jr

Barbara S DeWitt

Hanyi Ding

B M Farid Rahman

William Piper

Bm Farid Rahman

Kai D Feng

Pinping Sun

Amit Bavisi

The disclosure is directed to semiconductor structures and, more particularly, to a three dimensional microstrip branchline coupler and methods of manufacture. The structure includes a plurality of through silicon vias and conductive lines electrically connected to a first end and a second end of respective ones of the plurality of through silicon vias. A first through silicon via of the plurality of through silicon vias forms a first port of a three dimensional (3D) branchline coupler. A second through silicon via of the plurality of through silicon vias forms a second port of the 3D branchline coupler. A third through silicon via of the plurality of through silicon vias forms a third port of the 3D branchline coupler. A fourth through silicon via of the plurality of through silicon vias forms a fourth port of the 3D branchline coupler.

3D-microstrip branchline coupler

A vertical three dimensional (3D) microstrip line structure for improved tunable characteristic impedance, methods of manufacturing the same and design structures are provided. More specifically, a method is provided that includes forming a first microstrip line structure within a back end of the line (BEOL) stack. The method further includes forming a second microstrip line structure separated from the BEOL stack by a predetermined horizontal distance.

On-chip vertical three dimensional microstrip line with characteristic impedance tuning technique and design structures

A high performance on-chip vertical coaxial cable structure, method of manufacturing and design structure thereof is provided. The coaxial cable structure includes an inner conductor and an insulating material that coaxially surrounds the inner conductor. The structure further includes an outer conductor which surrounds the insulating material. Both the inner and outer conductors comprise a plurality of metal layers formed on different wiring levels and interconnected between the different wiring levels by conductors. The coaxial cable structure is formed upon a surface of a semiconductor substrate and is oriented in substantially perpendicular alignment with the surface.

High performance on-chip vertical coaxial cable, method of manufacture and design structure

A three dimensional (3D) branchline coupler using through silicon vias (TSV), methods of manufacturing the same and design structures are disclosed. The method includes forming a first waveguide structure in a first dielectric material. The method further includes forming a second waveguide structure in a second dielectric material. The method further includes forming through silicon vias through a substrate formed between the first dielectric material and the second dielectric material, which connects the first waveguide structure to the second waveguide structure.

Three dimensional branchline coupler using through silicon vias and design structures

On-chip, high performance, slow-wave coplanar waveguide with through-silicon via structures, method of manufacture and design structures for integrated circuits are provided herein. The method includes forming at least one ground plane layer in a substrate and forming a signal layer in the substrate, in a same plane layer as the at least one ground. The method further includes forming at least one metal filled through-silicon via between the at least one ground plane layer and the signal layer.

On-chip slow-wave through-silicon via coplanar waveguide structures, method of manufacture and design structure

A methodology for developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure is disclosed. The method is implemented on a computing device and includes generating a model for effects of metal fill in an integrated circuit. The metal fill model is generated prior to completion of a layout design for the integrated circuit.

Methodology on developing metal fill as library device

On-chip high performance slow-wave coplanar waveguide structures, method of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and a signal layer provided in a same plane as the at least one ground. The signal layer has at least one alternating wide portion and narrow portion. The wide portion extends toward the at least one ground.

Coplanar waveguide structures with alternating wide and narrow portions, method of manufacture and design structure

On-chip high performance slow-wave microstrip line structures, methods of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and a signal layer provided in a different plane than the at least one ground. The signal layer has at least one alternating wide portion and narrow portion with an alternating thickness such that a height of the wide portion is different than a height of the narrow portion with respect to the at least one ground.

Microstrip line structures with alternating wide and narrow portions having different thicknesses relative to ground, method of manufacture and design structures

On-chip high performance slow-wave coplanar waveguide structures, method of manufacture and design structures for integrated circuits are provided herein. The structure includes at least one ground and signal layer provided in a same plane as the at least one ground. The signal layer has at least one alternating wide portion and narrow portion with an alternating thickness. The wide portion extends toward the at least one ground.

Coplanar waveguide structures with alternating wide and narrow portions having different thicknesses, method of manufacture and design structure

A methodology is provided on developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure. The method is implemented on a computing device and includes generating a model for effects of metal fill in an integrated circuit. The metal fill model is generated prior to completion of a layout design for the integrated circuit.

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South Burlington, VT, United States of America

Essam Mina