Intel Corporation

Mellanox Technologies, Ltd.

Mellanox Technologies Tlv Ltd.

Eshel Gordon

Ofir Degani

Igal Kushnir

Rotem Banin

Shilpa Talwar

Kameran Azadet

Hosein Nikopour

Bryan K Casper

Wook Bong Lee

Ashoke Ravi

Michael Genossar

Claudio Da Silva

Stefano Pellerano

Debabani Choudhury

Albert Molina

Sidharth Dalmia

Georgios Yorgos Palaskas

Duncan Kitchin

Saku Lahti

Oner Orhan

Emanuel Cohen

Gadi Shor

Mikko S Komulainen

Jayprakash Thakur

Eren Sasoglu

Arnaud Lucres Amadjikpe

Kunal Datta

Menashe Soffer

Ana M Yepes

Moshe Teplitsky

Omer Asaf

Run Levinger

Chintan S Thakkar

Josef Hagn

Erkan Alpman

Nebil Tanzi

Ron Pongratz

Tawfiq Musah

Baljit Singh

Peter Sagazio

Eyal Goldberger

Amit Freiman

Shuhei Yamada

Kaushik Dasgupta

Eran Gerson

Shmuel Ravid

Yossi Tsfati

Marian K Verhelst

Meir Gordon

Anandaroop Chakrabarti

Resti Montoya Moreno

Roi Levi

Noam Kogan

Nir Weisman

Naftali Landsberg

Ra'anan Sover

Mikko M Lampinen

Miroslav Baryakh

Avi Tsarfati

Lior Shakedd

Anat Bazov

Stefano Brenna

Saeid Daneshgar Asl

Amr M Fahim

Shinwon Kang

Te Yu Kao

Nathan G Narevsky

Sarit Zur

Gregory Chance

Brandon Davis

Hasnain Lakdawala

Michael Kerner

Elan Banin

Assaf Ben-Bassat

Evgeny Shumaker

Gil Horovitz

Gregory W Chance

Rotem Avivi

Brandon R Davis

Sebastian Sievert

Ofer Benjamin

Aryeh Farber

Ayal Eshkoli

Yair Dgani

Boris Sharav

Semyon Lebedev

Tami Sela

Sophia Maerkovich

A digital-to-charge converter, a digital-to-analog converter, and a method of operating a digital-to-charge converter are provided. An illustrative method of operating a digital-to-charge converter is provided that includes: receiving a digital input signal at the digital to charge converter, charging one or more capacitors during a pre-evaluation period, where the one or more capacitors are charged with a supply voltage based the digital input signal, disconnecting the one or more capacitors from the supply voltage during an evaluation period, and generating an analog output signal from the digital to charge converter based on an evaluation of charge of the one or more capacitors during the evaluation period.

High speed charge mode digital-to-analog converter

Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

Wireless communication technology, apparatuses, and methods

A digital to analog converter (DAC) includes a first amplifier configured to receive a first bit of a data block as an input and output a first signal based on a value of the first bit of the data block, a first filter circuit configured to filter the first signal, an output configured to output an analog signal based on a combination of the filtered first signal and a second signal that represents a value of a second bit of the data block.

Systems, methods, and devices for digital-to-analog conversion in data transmission

An apparatus for regulating a supply voltage supplied from a voltage source to a load via a supply line is provided. The apparatus includes a control circuit configured to generate a control signal based on a difference between a value of the supply voltage and a nominal value of the supply voltage. Further, the apparatus includes a switch circuit configured to couple a charged capacitive element to the supply line based on the control signal.

Apparatus and method for regulating a supply voltage

A data modulator for a transmitter includes a multiplexer configured to receive, at a first rate, a first data stream including a plurality of first symbols and a second data stream including a plurality of second symbols. The multiplexer is configured to selectively output, based on a first clock signal, the plurality of first symbols and the plurality of second symbols to form a third data stream that achieves a second rate greater than the first rate for transmission of the third data stream by the transmitter.

Systems, methods, and devices for high-speed data modulation

A time-to-digital converter is provided. The time-to-digital converter includes a delay circuit configured to iteratively delay a reference signal for generating a plurality of delayed reference signals. Further, the time-to-digital converter includes a plurality of sample circuits each configured to sample an oscillation signal based on one of the plurality of delayed reference signals. The time-to-digital converter additionally includes a control circuit configured to de-activate at least one of the plurality of sample circuits based on a predicted value of the phase of the oscillation signal.

Time-to-digital converter, digital phase-locked loop, method for operating a time-to-digital converter, and method for a digital phase-locked loop

An apparatus for a low-power radar detection (LPRD) receiver is proposed in this disclosure. The LPRD receiver comprises an analog-to-digital converter (ADC) circuit configured to receive an analog dynamic frequency selection (DFS) signal associated with a DFS channel in a DFS frequency band to generate a digital DFS signal. The ADC circuit comprises a finite impulse response (FIR) filter circuit configured to sample the analog DFS signal at an FIR sampling rate determined based on a predetermined frequency plan associated with the DFS frequency band to generate a sampled DFS signal; and an ADC conversion circuit configured to convert the sampled DFS signal to the digital DFS signal at an ADC conversion rate that is lower than the FIR sampling rate.

Unique frequency plan and baseband design for low power radar detection module

Some embodiments include apparatuses and methods using capacitor circuitry to sample a value of an input signal; comparators to compare the value of the input signal with a range of voltage values and provide comparison results; successive approximation register (SAR) logic circuitry to generate first bits and second bits based on the comparison results; and circuitry to calculate an average value of a value of the second bits and a value of bits of a portion of the first bits, and to generate output bits representing the value of the input signal, the output bits including bits generated based on the average value.

Scalable stochastic successive approximation register analog-to-digital converter

An apparatus comprises a radio frequency (RF) transceiver circuit; a phase modulator that comprises digital-to-time converter (DTC) circuitry configured to convert a digital value to a specified signal phase of a signal transmitted by the RF transceiver circuit; low drop out regulator (LDO) circuitry operatively coupled to the DTC circuitry, wherein a bias current of the LDO circuitry is adjustable; and logic circuitry operatively coupled to the LDO circuitry and DTC circuitry, wherein the logic circuitry is configured to set the adjustable bias current of the LDO circuitry according to a digital value input to the DTC circuitry.

Low drop out compensation technique for reduced dynamic errors in digital-to-time converters

A fully differential amplifier having a start-up circuit is described. The fully differential amplifier may be a two-stage amplifier with a start-up circuit coupled between the stages. The start-up circuit may include a sense circuit coupled between a common mode input and internal nodes that are connect to output transistors of the fully differential amplifier. The sense circuit produces a reset signal that forces the fully differential amplifier into a mode of operation.

Fully differential amplifier with start up circuit

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Aloney Aba, Israel

Eshel Gordon